3.6.1 Description

DDR-SDRAM Controller (MPDDRC) maximizes memory bandwidth and minimizes transaction latency due to the DDR-SDRAM protocol.

The MPDDRC extends the memory capabilities of a chip by providing the interface to the external 16-bit DDR-SDRAM device. The page size supports ranges from 2048 to 16384 rows and from 512 to 4096 columns. It supports word (32-bit), half-word (16-bit), and byte (8-bit) accesses.

The MPDDRC supports a read or write burst length of eight locations. This enables the command and address bus to anticipate the next command, thus reducing latency imposed by the DDR-SDRAM protocol and improving the DDR-SDRAM bandwidth. Moreover, MPDDRC keeps track of the active row in each bank, thus maximizing DDR-SDRAM performance, e.g., the application may be placed in one bank and data in other banks. To optimize performance, avoid accessing different rows in the same bank. The MPDDRC supports a CAS latency of 3, 4, 5 or 6 and optimizes the read access depending on the frequency.

Self-Refresh and Power-Down modes minimize the consumption of the DDR-SDRAM device.

OCD (Off-chip Driver) and ODT (On-die Termination) modes, and Write Leveling, are not supported.

The MPDDRC supports DDR3-SDRAM and DDR3L-SDRAM devices with DLL disabled (DLL Off) and DLL enabled (DLL On).

In DLL Off mode, as per the applicable JEDEC standard, the maximum clock frequency is 125 MHz. However, check with memory suppliers for support for higher speeds. The DLL Off mode sets the CAS Read Latency (CRL) and the CAS Write Latency (CWL) to 6.

In DLL On mode, as per the applicable JEDEC standard, the minimum clock frequency is 303 MHz. However, check with memory suppliers for support for lower speeds. The DLL On mode sets the CAS Read Latency (CRL) to 6 and the CAS Write Latency (CWL) to 5. DDR3-SDRAM supports high-capacity (1 Gbit and greater) and can reduce power consumption with a 1.5V supply (DDR3-SDRAM) or a 1.35V supply (DDR3L-SDRAM).