Compliant with Inter-IC Sound (I2S) Bus Specification
Host, Client, and Controller Modes
Client: Data received/transmitted
Host: Data received/transmitted and clocks generated
Controller: Clocks generated
Individual Enable and Disable of Receiver, Transmitter and Clocks
Configurable Clock Generator Common to Receiver and Transmitter
Suitable for a wide range of sample frequencies (fs), including 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96
kHz, and 192 kHz
16 fs to 1024 fs host clock generated for external oversampling data converters
Support for Multiple Data Formats
32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format
16- and 8-bit compact stereo format, with left and right samples
packed in the same word to reduce data transfers
Support for Multiple Data Frame Formats
2-channel I2S with word select
1- to 8-channel Time Division Multiplexed (TDM) with frame
synchronization
DMA Controller Interfaces the Receiver
and Transmitter to Reduce Processor Overhead
Smart Holding Registers Management to Avoid Audio Channel Mix After
Overrun or Underrun
Functional Safety Monitors and
Reports
Internal sequencer integrity check
reports
Register write protection
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
