Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
4 System Controller
5 Image Subsystem
- 5.1 Overview
- 5.2 LCD Controller (LCDC)
  - 5.2.1 Description
  - 5.2.2 Embedded Characteristics
  - 5.2.3 Block Diagram
  - 5.2.4 I/O Lines Description
  - 5.2.5 Product Dependencies
  - 5.2.6 Functional Description
  - 5.2.7 Register Summary
    - 5.2.7.1 LCDC Configuration Register 0
      LCDC Configuration Register 0
    - 5.2.7.2 LCDC Configuration Register 1
      LCDC Configuration Register 1
    - 5.2.7.3 LCDC Configuration Register 2
      LCDC Configuration Register 2
    - 5.2.7.4 LCDC Configuration Register 3
      LCDC Configuration Register 3
    - 5.2.7.5 LCDC Configuration Register 4
      LCDC Configuration Register 4
    - 5.2.7.6 LCDC Configuration Register 5
      LCDC Configuration Register 5
    - 5.2.7.7 LCDC Configuration Register 6
      LCDC Configuration Register 6
    - 5.2.7.8 LCDC Configuration Register 7
      LCDC Configuration Register 7
    - 5.2.7.9 LCDC Enable Register
      LCDC Enable Register
    - 5.2.7.10 LCDC Disable Register
      LCDC Disable Register
    - 5.2.7.11 LCDC Status Register
      LCDC Status Register
    - 5.2.7.12 LCDC Interrupt Enable Register
      LCDC Interrupt Enable Register
    - 5.2.7.13 LCDC Interrupt Disable Register
      LCDC Interrupt Disable Register
    - 5.2.7.14 LCDC Interrupt Mask Register
      LCDC Interrupt Mask Register
    - 5.2.7.15 LCDC Interrupt Status Register
      LCDC Interrupt Status Register
    - 5.2.7.16 LCDC Attribute Enable Register
      LCDC Attribute Enable Register
    - 5.2.7.17 LCDC Attribute Status Register
      LCDC Attribute Status Register
    - 5.2.7.18 Base Layer Interrupt Enable Register
      Base Layer Interrupt Enable Register
    - 5.2.7.19 Base Layer Interrupt Disable Register
      Base Layer Interrupt Disable Register
    - 5.2.7.20 Base Layer Interrupt Mask Register
      Base Layer Interrupt Mask Register
    - 5.2.7.21 Base Layer Interrupt Status Register
      Base Layer Interrupt Status Register
    - 5.2.7.22 Base Layer Enable Register
      Base Layer Enable Register
    - 5.2.7.23 Base Layer Color Look-Up Table Address Register
      Base Layer Color Look-Up Table Address Register
    - 5.2.7.24 Base Layer Frame Buffer Address Register
      Base Layer Frame Buffer Address Register
    - 5.2.7.25 Base Layer Configuration Register 0
      Base Layer Configuration Register 0
    - 5.2.7.26 Base Layer Configuration Register 1
      Base Layer Configuration Register 1
    - 5.2.7.27 Base Layer Configuration Register 2
      Base Layer Configuration Register 2
    - 5.2.7.28 Base Layer Configuration Register 3
      Base Layer Configuration Register 3
    - 5.2.7.29 Base Layer Configuration Register 4
      Base Layer Configuration Register 4
    - 5.2.7.30 Base Layer Configuration Register 5
      Base Layer Configuration Register 5
    - 5.2.7.31 Base Layer Configuration Register 6
      Base Layer Configuration Register 6
    - 5.2.7.32 LCDC Write Protection Mode Register
      LCDC Write Protection Mode Register
    - 5.2.7.33 LCDC Write Protection Status Register
      LCDC Write Protection Status Register
    - 5.2.7.34 Overlay 1 Interrupt Enable Register
      Overlay 1 Interrupt Enable Register
    - 5.2.7.35 Overlay 1 Interrupt Disable Register
      Overlay 1 Interrupt Disable Register
    - 5.2.7.36 Overlay 1 Interrupt Mask Register
      Overlay 1 Interrupt Mask Register
    - 5.2.7.37 Overlay 1 Interrupt Status Register
      Overlay 1 Interrupt Status Register
    - 5.2.7.38 Overlay 1 Enable Register
      Overlay 1 Enable Register
    - 5.2.7.39 Overlay 1 Color Look-Up Table Address Register
      Overlay 1 Color Look-Up Table Address Register
    - 5.2.7.40 Overlay 1 Frame Buffer Address Register
      Overlay 1 Frame Buffer Address Register
    - 5.2.7.41 Overlay 1 Configuration Register 0
      Overlay 1 Configuration Register 0
    - 5.2.7.42 Overlay 1 Configuration Register 1
      Overlay 1 Configuration Register 1
    - 5.2.7.43 Overlay 1 Configuration Register 2
      Overlay 1 Configuration Register 2
    - 5.2.7.44 Overlay 1 Configuration Register 3
      Overlay 1 Configuration Register 3
    - 5.2.7.45 Overlay 1 Configuration Register 4
      Overlay 1 Configuration Register 4
    - 5.2.7.46 Overlay 1 Configuration Register 5
      Overlay 1 Configuration Register 5
    - 5.2.7.47 Overlay 1 Configuration Register 6
      Overlay 1 Configuration Register 6
    - 5.2.7.48 Overlay 1 Configuration Register 7
      Overlay 1 Configuration Register 7
    - 5.2.7.49 Overlay 1 Configuration Register 8
      Overlay 1 Configuration Register 8
    - 5.2.7.50 Overlay 1 Configuration Register 9
      Overlay 1 Configuration Register 9
    - 5.2.7.51 Overlay 2 Interrupt Enable Register
      Overlay 2 Interrupt Enable Register
    - 5.2.7.52 Overlay 2 Interrupt Disable Register
      Overlay 2 Interrupt Disable Register
    - 5.2.7.53 Overlay 2 Interrupt Mask Register
      Overlay 2 Interrupt Mask Register
    - 5.2.7.54 Overlay 2 Interrupt Status Register
      Overlay 2 Interrupt Status Register
    - 5.2.7.55 Overlay 2 Enable Register
      Overlay 2 Enable Register
    - 5.2.7.56 Overlay 2 Color Look-Up Table Register
      Overlay 2 Color Look-Up Table Register
    - 5.2.7.57 Overlay 2 Frame Buffer Address Register
      Overlay 2 Frame Buffer Address Register
    - 5.2.7.58 Overlay 2 Configuration Register 0
      Overlay 2 Configuration Register 0
    - 5.2.7.59 Overlay 2 Configuration Register 1
      Overlay 2 Configuration Register 1
    - 5.2.7.60 Overlay 2 Configuration Register 2
      Overlay 2 Configuration Register 2
    - 5.2.7.61 Overlay 2 Configuration Register 3
      Overlay 2 Configuration Register 3
    - 5.2.7.62 Overlay 2 Configuration Register 4
      Overlay 2 Configuration Register 4
    - 5.2.7.63 Overlay 2 Configuration Register 5
      Overlay 2 Configuration Register 5
    - 5.2.7.64 Overlay 2 Configuration Register 6
      Overlay 2 Configuration Register 6
    - 5.2.7.65 Overlay 2 Configuration Register 7
      Overlay 2 Configuration Register 7
    - 5.2.7.66 Overlay 2 Configuration Register 8
      Overlay 2 Configuration Register 8
    - 5.2.7.67 Overlay 2 Configuration Register 9
      Overlay 2 Configuration Register 9
    - 5.2.7.68 High-End Overlay Interrupt Enable Register
      High-End Overlay Interrupt Enable Register
    - 5.2.7.69 High-End Overlay Interrupt Disable Register
      High-End Overlay Interrupt Disable Register
    - 5.2.7.70 High-End Overlay Interrupt Mask Register
      High-End Overlay Interrupt Mask Register
    - 5.2.7.71 High-End Overlay Interrupt Status Register
      High-End Overlay Interrupt Status Register
    - 5.2.7.72 High-End Overlay Enable Register
      High-End Overlay Enable Register
    - 5.2.7.73 High-End Overlay Color Look-Up Table Address Register
      High-End Overlay Color Look-Up Table Address Register
    - 5.2.7.74 High-End Overlay Frame Buffer Address Register
      High-End Overlay Frame Buffer Address Register
    - 5.2.7.75 High-End Overlay Cb Plane Frame Buffer Address Register
      High-End Overlay Cb Plane Frame Buffer Address Register
    - 5.2.7.76 High-End Overlay Cr Plane Frame Buffer Address Register
      High-End Overlay Cr Plane Frame Buffer Address Register
    - 5.2.7.77 High-End Overlay Frame Buffer 1 Address Register
      High-End Overlay Frame Buffer 1 Address Register
    - 5.2.7.78 High-End Overlay Cb Plane Frame Buffer 1 Address Register
      High-End Overlay Cb Plane Frame Buffer 1 Address Register
    - 5.2.7.79 High-End Overlay Cr Plane Frame Buffer 1 Address Register
      High-End Overlay Cr Plane Frame Buffer 1 Address Register
    - 5.2.7.80 High-End Overlay Configuration Register 0
      High-End Overlay Configuration Register 0
    - 5.2.7.81 High-End Overlay Configuration Register 1
      High-End Overlay Configuration Register 1
    - 5.2.7.82 High-End Overlay Configuration Register 2
      High-End Overlay Configuration Register 2
    - 5.2.7.83 High-End Overlay Configuration Register 3
      High-End Overlay Configuration Register 3
    - 5.2.7.84 High-End Overlay Configuration Register 4
      High-End Overlay Configuration Register 4
    - 5.2.7.85 High-End Overlay Configuration Register 5
      High-End Overlay Configuration Register 5
    - 5.2.7.86 High-End Overlay Configuration Register 6
      High-End Overlay Configuration Register 6
    - 5.2.7.87 High-End Overlay Configuration Register 7
      High-End Overlay Configuration Register 7
    - 5.2.7.88 High-End Overlay Configuration Register 8
      High-End Overlay Configuration Register 8
    - 5.2.7.89 High-End Overlay Configuration Register 9
      High-End Overlay Configuration Register 9
    - 5.2.7.90 High-End Overlay Configuration Register 10
      High-End Overlay Configuration Register 10
    - 5.2.7.91 High-End Overlay Configuration Register 11
      High-End Overlay Configuration Register 11
    - 5.2.7.92 High-End Overlay Configuration Register 12
      High-End Overlay Configuration Register 12
    - 5.2.7.93 High-End Overlay Configuration Register 13
      High-End Overlay Configuration Register 13
    - 5.2.7.94 High-End Overlay Configuration Register 14
      High-End Overlay Configuration Register 14
    - 5.2.7.95 High-End Overlay Configuration Register 15
      High-End Overlay Configuration Register 15
    - 5.2.7.96 High-End Overlay Configuration Register 16
      High-End Overlay Configuration Register 16
    - 5.2.7.97 High-End Overlay Configuration Register 17
      High-End Overlay Configuration Register 17
    - 5.2.7.98 High-End Overlay Configuration Register 18
      High-End Overlay Configuration Register 18
    - 5.2.7.99 High-End Overlay Configuration Register 19
      High-End Overlay Configuration Register 19
    - 5.2.7.100 High-End Overlay Configuration Register 20
      High-End Overlay Configuration Register 20
    - 5.2.7.101 High-End Overlay Configuration Register 21
      High-End Overlay Configuration Register 21
    - 5.2.7.102 High-End Overlay Configuration Register 22
      High-End Overlay Configuration Register 22
    - 5.2.7.103 High-End Overlay Configuration Register 23
      High-End Overlay Configuration Register 23
    - 5.2.7.104 High-End Overlay Configuration Register 24
      High-End Overlay Configuration Register 24
    - 5.2.7.105 High-End Overlay Configuration Register 25
      High-End Overlay Configuration Register 25
    - 5.2.7.106 High-End Overlay Configuration Register 26
      High-End Overlay Configuration Register 26
    - 5.2.7.107 High-End Overlay Configuration Register 27
      High-End Overlay Configuration Register 27
    - 5.2.7.108 High-End Overlay Configuration Register 28
      High-End Overlay Configuration Register 28
    - 5.2.7.109 High-End Overlay Configuration Register 29
      High-End Overlay Configuration Register 29
    - 5.2.7.110 High-End Overlay Configuration Register 30
      High-End Overlay Configuration Register 30
    - 5.2.7.111 High-End Overlay Configuration Register 31
      High-End Overlay Configuration Register 31
    - 5.2.7.112 High-End Overlay Vertical Scaler Taps 1 and 0 Phase x Register
      High-End Overlay Vertical Scaler Taps 1 and 0 Phase x Register
    - 5.2.7.113 High-End Overlay Vertical Scaler Taps 3 and 2 Phase x Register
      High-End Overlay Vertical Scaler Taps 3 and 2 Phase x Register
    - 5.2.7.114 High-End Overlay Horizontal Scaler Taps 1 and 0 Phase x Register
      High-End Overlay Horizontal Scaler Taps 1 and 0 Phase x Register
    - 5.2.7.115 High-End Overlay Horizontal Scaler Taps 3 and 2 Phase x Register
      High-End Overlay Horizontal Scaler Taps 3 and 2 Phase x Register
    - 5.2.7.116 Base Layer CLUT Register x
      Base Layer CLUT Register x
    - 5.2.7.117 Overlay 1 CLUT Register x
      Overlay 1 CLUT Register x
    - 5.2.7.118 Overlay 2 CLUT Register x
      Overlay 2 CLUT Register x
    - 5.2.7.119 High-End Overlay CLUT Register x
      High-End Overlay CLUT Register x
- 5.3 Low Voltage Differential Signaling Controller (LVDSC)
- 5.4 2D Graphics Engine (GFX2D)
- 5.5 Display Serial Interface (DSI)
- 5.6 Camera Serial Interface (CSI)
- 5.7 CSI-2 Demultiplexer Controller (CSI2DC)
- 5.8 Image Sensor Controller (ISC)
6 Audio Subsystem
7 Security and Cryptography Subsystem
8 Connectivity Subsystem
9 USB Subsystem
10 Electrical and Mechanical Characteristics
11 Revision History
Microchip Information

5.2.7.15 LCDC Interrupt Status Register

Name:	LCDC_LCDISR
Offset:	0x00000038
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24
	WP
Access	R
Reset	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					HEO	OVR2	OVR1	BASE
Access					R	R	R	R
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
				FIFOERR	ROW	DISP	DIS	SOF
Access				R	R	R	R	R
Reset				0	0	0	0	0

Bit 31 – WP Write Protection Interrupt Status

Value	Description
0	No Write Protection interrupt detected since last read of LCDC_LCDISR.
1	Indicates that a Write Protection error has been detected. This flag is reset after a read operation.

Bit 11 – HEO High-End Overlay Raw Interrupt Status

Value	Description
0	No High-End layer interrupt detected since last read of LCDC_HEOISR.
1	Indicates that a High-End layer interrupt is pending. This flag is reset as soon as the LCDC_HEOISR is read.

Bit 10 – OVR2 Overlay 2 Raw Interrupt Status

Value	Description
0	No Overlay 2 layer interrupt detected since last read of LCDC_OVR2ISR.
1	Indicates that an Overlay 2 layer interrupt is pending. This flag is reset as soon as the LCDC_OVR2ISR is read.

Bit 9 – OVR1 Overlay 1 Raw Interrupt Status

Value	Description
0	No Overlay 1 layer interrupt detected since last read of LCDC_OVR1ISR.
1	Indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the LCDC_OVR1ISR is read.

Bit 8 – BASE Base Layer Raw Interrupt Status

Value	Description
0	No base layer interrupt detected since last read of LCDC_BASEISR.
1	Indicates that a base layer interrupt is pending. This flag is reset as soon as the LCDC_BASEISR is read.

Bit 4 – FIFOERR Output FIFO Error

Value	Description
0	No underflow has occurred in the output FIFO since last read of LCDC_LCDISR.
1	Indicates that an underflow has occurred in the output FIFO. This flag is reset after a read operation.

Bit 3 – ROW Row Interrupt Status

Value	Description
0	No detection since last read of the LCDC_LCDCISR.
1	Indicates that a row event has been detected. This flag is reset after a read operation.

Bit 2 – DISP Power-up/Power-down Sequence Terminated Interrupt Status

Value	Description
0	Power-up sequence or power-down sequence has not yet terminated.
1	Indicates the power-up sequence or power-down sequence has terminated. This flag is reset after a read operation.

Bit 1 – DIS LCD Disable Interrupt Status

Value	Description
0	Horizontal and vertical timing generator has not yet been disabled.
1	Indicates that the horizontal and vertical timing generator has been disabled. This flag is reset after a read operation.

Bit 0 – SOF Start of Frame Interrupt Status

Value	Description
0	No detection since last read of LCDC_LCDISR.
1	Indicates that a start of frame event has been detected. This flag is reset after a read operation.

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