4.13.5.7 Debug Communication Channel Support

The DBGU handles the COMMRX and COMMTX signals that come from the Debug Communication Channel of the Arm processor and are driven by the In-circuit Emulator.

The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the Arm processor side.

As a reminder, the following instructions are used to read and write the Debug Communication Channel:

MRC p14, 0, Rd, c1, c0, 0

Returns the debug communication data read register into Rd.

MCR p14, 0, Rd, c1, c0, 0

Writes the value in Rd to the debug communication data write register.

The COMMRX and COMMTX bits which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of DBGU_SR. These bits can generate an interrupt. This feature can be used to handle under interrupt a debug link between a debug monitor running on the target system and a debugger.