4.17.13 Recommended Programming Sequence

Follow the steps below to program the PMC:

  1. If the main crystal oscillator is not required, the PLL can be directly configured (step 5) else this oscillator must be started (step 2).
  2. Verify the existence and frequency value of the main crystal oscillator following the sequence defined in Main Frequency Counter.
  3. If the main crystal oscillator is enabled and valid, the source of MAINCK can be switched to the main crystal oscillator by writing CKGR_MOR.MOSCSEL to 1 else the PLL can be directly configured.
  4. Wait for the end of the MAINCK source switching by either polling the MOSCSELS or setting the corresponding interrupt.
  5. Configure the PLLs by following the setup defined in Divider and Phase Lock Loop Programming (if not required, proceed to step 6).
  6. Configure the MCK division ratio by setting PMC_CPU_CKR.MDIV. Available values are 0, 1, 2, 3, 4. MCK output is the CPU_CLK frequency divided by 1, 2, 3, 4 or 5, depending on the value programmed in MDIV.

    By default, MDIV is cleared, which indicates that the CPU_CLK is equal to MCK.

  7. Wait for the end of the MCK ratio switching by either polling the MCKRDY or setting the corresponding interrupt.
  8. Select the division ratio of CPU_CLK by setting PMC_CPU_CKR.PRES.

    PRES is used to define the CPU_CLK and MCK prescaler. The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value.

  9. Wait for the end of the CPU_CLK ratio switching by either polling the MCKRDY or setting the corresponding interrupt.
  10. Select the source clock of CPU_CLK by setting PMC_CPU_CKR.CSS.

    CSS is used to select the clock source of MCK and CPU_CLK. By default, the selected clock source is MAINCK.

  11. Wait for the end of the CPU_CLK source switching by either polling the MCKRDY or setting the corresponding interrupt.

    PMC_CPU_CKR must not be programmed in a single write operation.

    Reconfiguring MDIV, PRES and CSS fields must always be done by following the right order of operation described above (steps 6 to 11).

  12. Configure the programmable clocks (PCKx):

    PCKx are controlled via registers PMC_SCER, PMC_SCDR and PMC_SCSR.

    PCKx can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Two PCKx can be used. PMC_SCSR indicates which PCKx is enabled. By default all PCKx are disabled.

    PMC_PCKx registers are used to configure PCKx as described in Programmable Clock Output Controller.

  13. Enable the peripheral and generic clocks.

    Once all of the previous steps have been completed, the peripheral and generic clocks can be configured via register PMC_PCR as described in Peripheral and Generic Clock Controller.