7.2.5.21 AES Write Protection Mode Register

Name: AES_WPMR
Offset: 0xE4
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 WPKEY[23:16] 
Access WWWWWWWW 
Reset 00000000 
Bit 2322212019181716 
 WPKEY[15:8] 
Access WWWWWWWW 
Reset 00000000 
Bit 15141312111098 
 WPKEY[7:0] 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 ACTION[2:0]FIRSTE WPCRENWPITENWPEN 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 31:8 – WPKEY[23:0] Write Protection Key

ValueNameDescription
0x414553 PASSWD

Writing any other value in this field aborts the write operation of the WPEN,WPITEN,WPCREN bits.

Always reads as 0.

Bits 7:5 – ACTION[2:0] Action on Abnormal Event Detection

When the field AES_WPMR.ACTION differs from 0 and an abnormal event or internal state is detected, the AES is locked until the unlock command is issued (AES_CR.UNLOCK=1). The lock source must be cleared before performing the unlock command. If AES_WPSR.SEQE=1, the following two actions must be performed:

1/ Read AES_WPSR.

2/ Issue software reset by writing a 1 in AES_CR.SWRST.

A specific configuration applies where the sequence does not clear the lock source (AES_WPSR=0).

If AES_WPSR.SEQE remains high after the clearing sequence, then only a hardware reset will unlock the AES. A hardware reset can be performed by issuing a reset controller software reset (refer to the section “Reset Controller (RSTC)”). This condition can be met when AES_EMR.PKWL=1 and a key has been loaded through the Private Key bus. The key loaded through the key bus is corrupted, but it is impossible to reload a new key unless a hardware reset is issued.

ValueNameDescription
0 REPORT_ONLY

No action (stop or clear key) is performed when one of PKRPVS, WPVS, CGD, SEQE, or SWE flags is set.

1 LOCK_PKRPVS_WPVS_SWE

If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/SWE event detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.

2 LOCK_CGD_SEQE

If a processing is in progress when the AES_WPSR.CGD/SEQE event detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.

3 LOCK_ANY_EV

If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/CGD/SEQE/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.

4 CLEAR_PKRPVS_WPVS_SWE

If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.

Moreover, the AES_KEYWRx key is immediately cleared.

5 CLEAR_CGD_SEQE

If a processing is in progress when the AES_WPSR.CGD/SEQE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.

Moreover, the AES_KEYWRx key is immediately cleared.

6 CLEAR_ANY_EV

If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/CGD/SEQE/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.

Moreover, the AES_KEYWRx key is immediately cleared.

Bit 4 – FIRSTE First Error Report Enable

ValueDescription
0

The last write protection violation source is reported in AES_WPSR.WPVSRC and the last software control error type is reported in AES_WPSR.SWETYP. The AES_ISR.SECE flag is set at the first error occurrence within a series.

1

Only the first write protection violation source is reported in AES_WPSR.WPVSRC and only the first software control error type is reported in AES_WPSR.SWETYP. The AES_ISR.SECE flag is set at the first error occurrence within a series.

Bit 2 – WPCREN Write Protection Control Enable

ValueDescription
0

Disables the write protection on control register if WPKEY corresponds to 0x414553 (“AES” in ASCII).

1

Enables the write protection on control register if WPKEY corresponds to 0x414553 (“AES” in ASCII).

Bit 1 – WPITEN Write Protection Interruption Enable

ValueDescription
0

Disables the write protection on interrupt registers if WPKEY corresponds to 0x414553 (“AES” in ASCII).

1

Enables the write protection on interrupt registers if WPKEY corresponds to 0x414553 (“AES” in ASCII).

Bit 0 – WPEN Write Protection Configuration Enable

See Register Write Protection for the list of registers that can be write-protected.

ValueDescription
0

Disables the write protection on configuration registers if WPKEY corresponds to 0x414553 (“AES” in ASCII).

1

Enables the write protection on configuration registers if WPKEY corresponds to 0x414553 (“AES” in ASCII).