8.3.7.11.9 FIFO Overflow/Underflow Error

If the Transmit FIFO is full and a write access is performed on FLEX_US_THR, it generates a Transmit FIFO overflow error and sets FLEX_US_FESR.TXFPTEF.

If the number of data written in FLEX_US_THR (according to the register access size) is greater than the free space in the Transmit FIFO, a Transmit FIFO overflow error is generated and FLEX_US_FESR.TXFPTEF is set.

If the number of data read in FLEX_US_RHR (according to the register access size) is greater than the number of unread data in the Receive FIFO, a Receive FIFO underflow error is generated and FLEX_US_FESR.RXFPTEF is set.

No error occurs if the FIFO state/level is checked before writing/reading in FLEX_US_THR/FLEX_US_RHR. The FIFO state/level can be checked either with TXRDY, RXRDY, TXFL or RXFL. When such error occurs, other FIFO flags may not behave as expected; their states must be ignored.

If a Transmit FIFO overflow error occurs, a transmitter reset must be performed using FLEX_US_CR.RSTTX. If a Receive underflow error occurs, a receiver reset must be performed using FLEX_US_CR.RSTRX.