10.1.9.2 ULP0, ULP1 and Idle Modes

In these three low-power modes, the SAM9X7 Series power supplies are all applied within their operating range. The power reduction is achieved by reducing the frequency or even stopping the clock signals of the processor and/or its peripherals.

  • In Idle mode, only the processor clock is affected when in ULP0 and ULP1 modes; the clocks feeding both the processor and its peripherals are slowed down.
  • In ULP0 or ULP1 mode, the SAM9X7 Series is placed in Retention mode and is able to resume on wake- up events (any interrupt or hardware event). This mode is a combination of the Wait for Interrupt mode of the Arm core and the system clocks frequency reduction or shut-off.

A detailed description of each mode is provided in the following sections and is followed by a power consumption section dedicated to those modes.

ULP0 Operation

The ULP0 mode maintains very low frequency clocks (MCK, CPU_CLK) in the system to wake up on any interrupt. The selection of the clock frequency depends on the current consumption target versus the required wake-up time. The higher the frequency, the higher the power consumption and the faster the wake-up time.

The sequence to enter ULP0 mode is detailed below. The code used to enter this mode must be executed out of the internal SRAM0.

  1. Set the DDR to Self-refresh mode.
  2. Set the interrupts to wake up the system.
  3. Disable all peripheral clocks.
  4. Set the I/Os to an appropriate state and disable the USB transceivers.
  5. Switch the system clock to Slow Clock.
  6. Set the SRAM memories to Light Sleep mode in SFR_LS, except LS6 (internal SRAM).
  7. Disable the PLLs, the main oscillator and the 12 MHz RC oscillator.
  8. Enter the Wait for Interrupt mode and disable the CPU_CLK clock in PMC_SCDR.

Wake-up from ULP0 mode is triggered by any enabled interrupt. When resuming, the software reconfigures the system (oscillator, PLL, etc.) in the same state as before WFI. Disable Light Sleep mode for SRAM memories in the SFR_LS register prior to returning to full speed operation.

ULP1 Operation

Unlike the ULP0 mode, all the clocks are off in the ULP1 mode, and the number of wake-up sources is limited to the list below:

  • WKUP[13:0] pins (level transition, configurable debouncing)
  • RTC/RTT alarm
  • USB Resume from Suspend mode
  • Wake-On-LAN events from EMAC peripherals

The sequence to enter ULP1 mode is detailed below. The code used to enter this mode must be executed out of the internal SRAM0.

  1. Set the DDR to Self-refresh mode.
  2. Set the events to enable a system wake-up.
  3. Disable all peripheral clocks.
  4. Set the I/Os to an appropriate state and disable the USB transceivers.
  5. Switch the system clock to the 12 MHz RC oscillator.
  6. Set the SRAM memories to Light Sleep mode in SFR_LS, except LS6 (internal SRAM).
  7. Disable the PLLs and the main oscillator.
  8. Enter ULP1 mode by setting the ULP1 bit in CKGR_MOR and wait for the PMC_SR.MCKRDY bit to be set.

When resuming, the software reconfigures the system (oscillator, PLL, etc.) in the same state as before entering ULP1. In particular, the SRAM memories Light Sleep mode must be disabled as soon as possible in the wake-up process.

Idle Mode Operation

The purpose of Idle mode is to optimize power consumption of the device versus response time. In this mode, only the processor clock is stopped. The peripheral clocks, including the DDR controller clock, can be enabled. The current consumption in this mode is application-dependent.

This mode is entered via the Wait for Interrupt (WFI) instruction.

The processor can be awakened from an interrupt. The system resumes where it was before entering WFI mode.