2.12 WDT - Watchdog Timer

Both families are equipped with a Watchdog Timer (WDT) peripheral, but the feature and register sets are different. Thus, the software procedures that configure the megaAVR WDT operation must be fully replaced to support AVR Dx devices.

The watchdog of the megaAVR devices is clocked from an on-chip oscillator that runs at 1 MHz. The Watchdog Reset interval is selectable from 16 ms to 2.2 seconds using the Watchdog Timer Prescaler (WDP[2:0]) bits in the Watchdog Timer Control (WDTCTRL) register.

For the AVR Dx devices, the Watchdog module is improved and has an additional set of features. It operates asynchronously from the peripheral clock using an independent oscillator. It is clocked from an on-chip ultra-low power oscillator for improved power consumption and provides 11 selectable time-out intervals from 16 ms up to 8 seconds.

The WDT for both families has a write protection mechanism ensuring the WDT settings cannot be changed by accident. The following code examples show the Watchdog disable procedures:

void WDT_off(void)
{
    /* Reset WDT*/
    _WDR();
    /* Write logical one to WDTOE and WDE */
    WDTCR |= (1<<WDTOE) | (1<<WDE);
    /* Turn off WDT */
    WDTCR = 0x00;
}

void WDT_0_off(void)
{
    /* Reset WDT */    
    asm("WDR");
    /* Disable WDT */
    ccp_write_io((void *)&(WDT.CTRLA), 
                 WDT_PERIOD_OFF_gc     /* Off */
                 | WDT_WINDOW_OFF_gc   /* Off */);
}