2.3.2 SRAM and EEPROM Memories

For both families, the SRAM memory is located in the Data space. The address offset and the size of the SRAM memory can be different from device to device (even in the same family). Refer to the device data sheet for details about available size and address offset.

For the megaAVR devices, the EEPROM is located in a separate data space and is accessible through the I/O space. See the following code examples:

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
    /* Wait for completion of previous write */
    while(EECR & (1<<EEWE))
    ;
    /* Set up address and data registers */
    EEAR = uiAddress;
    EEDR = ucData;
    /* Write logical one to EEMWE */ 
    EECR |= (1<<EEMWE);
    /* Start eeprom write by setting EEWE */
    EECR |= (1<<EEWE);
}

The EEPROM is located in the Data space for the AVR Dx devices. That allows a linear addressing of the entire area and faster access using the LD/ST instructions:

uint8_t FLASH_0_read_eeprom_byte(eeprom_adr_t eeprom_adr)
{
	/* Read operation will be stalled by hardware if any write is in progress */
	return *(uint8_t *)(EEPROM_START + eeprom_adr);
}

nvmctrl_status_t FLASH_0_write_eeprom_byte(eeprom_adr_t eeprom_adr, uint8_t data)
{
	/* Wait for completion of previous operation */
	while (NVMCTRL.STATUS & (NVMCTRL_EEBUSY_bm | NVMCTRL_FBUSY_bm))
		;

	/* Program the EEPROM with desired value(s) */
	ccp_write_spm((void *)&NVMCTRL.CTRLA, NVMCTRL_CMD_EEERWR_gc);

	/* Write byte to EEPROM */
	*(uint8_t *)(EEPROM_START + eeprom_adr) = data;

	/* Clear the current command */
	ccp_write_spm((void *)&NVMCTRL.CTRLA, NVMCTRL_CMD_NONE_gc);

	return NVM_OK;
}