35.5.3 Clocks

The TCC bus clock (CLK_TCC0_APB) is enabled by default, and can be enabled and disabled in the Main Clock.

A generic clock (GCLK_TCC0) is required to clock the TCC. This clock must be configured and enabled in the generic clock controller before using the TCC.

The generic clocks (GCLK_TCC0) are asynchronous to the bus clock (CLK_TCC0_APB). Due to this asynchronicity, writing certain registers will require synchronization between the clock domains. Refer to 35.6.6 Synchronization for further details.