16.6.2.6 Peripheral Clock Masking

The user can disable or enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock Mask registers (APBxMASK) to '0' or '1'. The default state of the peripheral clocks is given in the table below:

Table 16-1. Peripheral Clock Default State
CPU Clock Domain
Peripheral ClockDefault State
CLK_AC_APBEnabled
CLK_ADC_APBEnabled
CLK_AES_APBEnabled
CLK_BRIDGE_A_AHBEnabled
CLK_BRIDGE_B_AHBEnabled
CLK_BRIDGE_C_AHBEnabled
CLK_CCL_APBEnabled
CLK_DMAC_AHBEnabled
CLK_DSU_AHBEnabled
CLK_EIC_APBEnabled
CLK_EVSYS_APBEnabled
CLK_FREQM_APBEnabled
CLK_GCLK_APBEnabled
CLK_MCLK_APBEnabled
CLK_NVMCTRL_AHBEnabled
CLK_NVMCTRL_APBEnabled
CLK_OSCCTRL_APBEnabled
CLK_PAC_AHBEnabled
CLK_PAC_APBEnabled
CLK_PORT_APBEnabled
CLK_PTC_APBEnabled
CLK_SERCOM0_APBEnabled
CLK_SERCOM1_APBEnabled
CLK_SERCOM2_APBEnabled
CLK_SERCOM3_APBEnabled
CLK_SERCOM4_APBEnabled
CLK_SERCOM5_APBEnabled
CLK_SLCD_APBEnabled
CLK_TC0_APBEnabled
CLK_TC1_APBEnabled
CLK_TC2_APBEnabled
CLK_TC3_APBEnabled
CLK_TCC0_APBEnabled
CLK_TRNG_APBEnabled
CLK_USB_AHBEnabled
CLK_USB_APBEnabled
CLK_WDT_APBEnabled
Table 16-2. Backup Clock Domain
Backup Clock Domain
Peripheral ClockDefault State
CLK_OSC32KCTRL_APBEnabled
CLK_PM_APBEnabled
CLK_SUPC_APBEnabled
CLK_RSTC_APBEnabled
CLK_RTC_APBEnabled

When the APB clock is not provided to a module, its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to '1'.

A module may be connected to several clock domains (for example, AHB and APB), in which case it will have several mask bits.

The clocks should only be switched off if it is certain that the module will not be used: Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash memory. Switching off the clock to the MCLK module (which contains the mask registers) or the corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.