33.8.2 Control B
| Name: | CTRLB |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected, Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ACKACT | CMD[1:0] | ||||||||
| Access | R/W | W | W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| QCEN | SMEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 18 – ACKACT Acknowledge Action
This bit defines the Client's acknowledge behavior after an address or data byte is received from the Host. The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled (CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read.
This bit is not enable-protected.
| Value | Description |
|---|---|
| 0 | Send ACK |
| 1 | Send NACK |
Bits 17:16 – CMD[1:0] Command
This bit field triggers the Client operation as the below. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the Client interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR.
All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given.
This bit is not enable-protected.
| CMD[1:0] | DIR | Action |
|---|---|---|
| 0x0 | X | (No action) |
| 0x1 | X | (Reserved) |
| 0x2 | Used to complete a transaction in response to a data interrupt (DRDY) | |
| 0 (Host write) | Execute acknowledge action succeeded by waiting for any start (S/Sr) condition | |
| 1 (Host read) | Wait for any start (S/Sr) condition | |
| 0x3 | Used in response to an address interrupt (AMATCH) | |
| 0 (Host write) | Execute acknowledge action succeeded by reception of next byte | |
| 1 (Host read) | Execute acknowledge action succeeded by Client data interrupt | |
| Used in response to a data interrupt (DRDY) | ||
| 0 (Host write) | Execute acknowledge action succeeded by reception of next byte | |
| 1 (Host read) | Execute a byte read operation followed by ACK/NACK reception | |
Bit 9 – QCEN Quick Command Enable
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Quick Command is disabled. |
| 1 | Quick Command is enabled. |
Bit 8 – SMEN Smart Mode Enable
When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read.
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Smart mode is disabled. |
| 1 | Smart mode is enabled. |