10.4.3 Configuration

Figure 10-1. Host-Client Relations High-Speed Bus Matrix

Table 10-4. High Speed Bus Matrix Hosts
High-Speed Bus Matrix Hosts	Host ID
CM0+ - Cortex M0+ Processor	0
DSU - Device Service Unit	1
DMAC - Direct Memory Access Controller / Data Access	2

Table 10-5. High-Speed Bus Matrix Clients
High-Speed Bus Matrix Clients	Client ID
Internal Flash Memory	0
SRAM Port 0 - CM0+ Access	1
SRAM Port 1 - DSU Access	2
AHB-APB Bridge B	3
AHB-APB Bridge A	4
AHB-APB Bridge C	5
SRAM Port 2 - DMAC Data Access	6

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