35.8.18 Compare/Capture Channel x

The CCx register represents the 16-, 24- or 32-bit value, CCx. The register has two functions, depending of the mode of operation.

For capture operation, this register represents the second buffer level and access point for the CPU and DMA.

For compare operation, this register is continuously compared to the counter value. Normally, the output form the comparator is then used for generating waveforms.

CCx register is updated with the buffer value from their corresponding CCBUFx register when an UPDATE condition occurs.

In addition, in match frequency operation, the CC0 register controls the counter period.

Name: CCx
Offset: 0x44 + x*0x04 [x=0..3]
Reset: 0x00000000
Property: Write-Synchronized

Bit 3130292827262524 
 CC25CC24CC23CC22CC21CC20CC19CC18 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 CC17CC16CC15CC14CC13CC12CC11CC10 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 CC9CC8CC7CC6CC5CC4CC3CC2 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CC1CC0DITHER[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – CCx Channel x Compare/Capture Value

These bits hold the value of the Channel x compare/capture register.

Note: When the TCC is configured as 16- or 24-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION Bits [31:m]
0x0 - NONE 31:0
0x1 - DITH4 31:4
0x2 - DITH5 31:5
0x3 - DITH6 31:6 (depicted)

Bits 5:0 – DITHER[5:0] Dithering Cycle Number

These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION Bits [n:0]
0x0 - NONE -
0x1 - DITH4 3:0
0x2 - DITH5 4:0
0x3 - DITH6 5:0 (depicted)