33.10.4 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
 ERROR     SBMB 
Access R/WR/WR/W 
Reset 000 

Bit 7 – ERROR Error Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.

ValueDescription
0 Error interrupt is disabled.
1 Error interrupt is enabled.

Bit 1 – SB Client on Bus Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Client on Bus Interrupt Enable bit, which disables the Client on Bus interrupt.

ValueDescription
0 The Client on Bus interrupt is disabled.
1 The Client on Bus interrupt is enabled.

Bit 0 – MB Host on Bus Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Host on Bus Interrupt Enable bit, which disables the Host on Bus interrupt.

ValueDescription
0 The Host on Bus interrupt is disabled.
1 The Host on Bus interrupt is enabled.