33.6.2.5 I2C Client Operation
The I2C Client is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by automatic handling of most events. The software driver complexity and code size are reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register (CTRLA.SMEN).
The I2C Client has two interrupt strategies.
When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit. In this mode, the I2C Client operates according to the following figure. The circles labelled "Sn" (S1, S2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction.
This diagram is used as reference for the description of the I2C Client operation throughout the document.
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in the following figure. This strategy can be used when it is not necessary to check DATA before acknowledging. For Host reads, an address and data interrupt will be issued simultaneously after the address acknowledge. However, for Host writes, the first data interrupt will be seen after the first data byte has been received by the Client and the acknowledge bit has been sent to the Host.
Receiving Address Packets (SCLSM=0)
When CTRLA.SCLSM=0, the I2C Client stretches the SCL line according to I2C Client Behavioral Diagram (SCLSM=0). When the I2C Client is properly configured, it will wait for a start condition.
When a start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected, and the I2C Client will wait for a new start condition. If the received address is a match, the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) will be set.
SCL will be stretched until the I2C Client clears INTFLAG.AMATCH. As the I2C Client holds the clock by forcing SCL low, the software has unlimited time to respond.
The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register (STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to the I2C Client had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. Therefore, the next AMATCH interrupt is the first indication of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C Host, one of two cases will arise based on transfer direction.
Case 1: Address packet accepted – Read flag set
The STATUS.DIR bit is ‘1’, indicating an I2C Host read operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, I2C Client hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), indicating data are needed for transmit. If a NACK is sent, the I2C Client will wait for a new start condition and address match.
Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C Client Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read and write operations as the command execution is dependent on the STATUS.DIR bit. Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Case 2: Address packet accepted – Write flag set
The STATUS.DIR bit is cleared, indicating an I2C Host write operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, the I2C Client will wait for data to be received. Data, repeated start or stop can be received.
If a NACK is sent, the I2C Client will wait for a new start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK. The I2C Client command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on STATUS.DIR.
Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Receiving Address Packets (SCLSM=1)
When SCLSM=1, the I2C Client will stretch the SCL line only after an ACK, see Client Behavioral Diagram (SCLSM=1). When the I2C Client is properly configured, it will wait for a start condition to be detected.
When a start condition is detected, the successive address packet will be received and checked by the address match logic.
If the received address is not a match, the packet will be rejected and the I2C Client will wait for a new start condition.
If the address matches, the acknowledge action as configured by the Acknowledge Action bit Control B register (CTRLB.ACKACT) will be sent and the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set. SCL will be stretched until the I2C Client clears INTFLAG.AMATCH. As the I2C Client holds the clock by forcing SCL low, the software is given unlimited time to respond to the address.
The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register (STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, the last packet addressed to the I2C Client had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C Host, INTFLAG.AMATCH be set to ‘1’ to clear it.
Receiving and Transmitting Data Packets
After the I2C Client has received an address packet, it will respond according to the direction either by waiting for the data packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C Client will send an acknowledge according to CTRLB.ACKACT.
Case 1: Data received
INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction.
Case 2: Data sent
When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received, indicated by STATUS.RXNACK=1, the I2C Client must expect a stop or a repeated start to be received. The I2C Client must release the data line to allow the I2C Host to generate a stop or repeated start. Upon detecting a stop condition, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C Client will return to IDLE state.
High-Speed Mode
When the I2C Client is configured in High-speed mode (Hs, CTRLA.SPEED=0x2) and CTRLA.SCLSM=1, switching between Full-speed and High-speed modes is automatic. When the Client recognizes a START followed by a Host code transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit (STATUS.HS). The Client will then remain in High-speed mode until a STOP is received.
10-Bit Addressing
When 10-bit addressing is enabled (ADDR.TENBITEN=1), the two address bytes following a START will be checked against the 10-bit Client address recognition. The first byte of the address will always be acknowledged, and the second byte will raise the address interrupt flag, see the following figure.
If the transaction is a write, then the 10-bit address will be followed by N data bytes.
If the operation is a read, the 10-bit address will be followed by a repeated START and
reception of '11110 ADDR[9:8] 1', and the second address interrupt will
be received with the DIR bit set. The Client matches on the second address as it it was
addressed by the previous 10-bit address.
PMBus Group Command
When the PMBus Group Command bit in the CTRLB register is set (CTRLB.GCMD=1) and 7-bit addressing is used, INTFLAG.PREC will be set when a STOP condition is detected on the bus. When CTRLB.GCMD=0, a STOP condition without address match will not be set INTFLAG.PREC.
The group command protocol is used to send commands to more than one device. The commands are sent in one continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the Clients addressed during the group command, they all begin executing the command they received.
The following figure shows an example where this Client, bearing ADDRESS 1, is addressed after a repeated START condition. There can be multiple Clients addressed before and after this Client. Eventually, at the end of the group command, a single STOP is generated by the Host. At this point a STOP interrupt is asserted.