12.2 GCLK cannot be stopped
If a speed mode other than DefaultSpeed or SDR12 is used, GCLK cannot be stopped, leading to unpredictable behavior.
Work Around
Perform an ALL soft reset before any operation to ensure the internal clock DLL can be stopped properly.
Affected Silicon Revisions
| A0 | A0-D1G | A0-D2G | A1 | A1-D1G | A1-D2G | ||||||
| X | X | X | X | X | X |