1 Silicon Issue Summary
In this table and in subsequent sections, the following applies:
- “X” means the silicon revision is affected by the erratum.
- “–” means the silicon revision is not affected by the erratum.
Module | Item/Feature | Affected Silicon Revisions | |
---|---|---|---|
A0 A0-D1G A0-D2G |
A1 A1-D1G A1-D2G | ||
ROM Code | Watchdog not disabled | X | X |
SHDWC | Wake-up events are not deactivated | X | X |
RTC | RTC_TSTR0 timestamping error | X | X |
PMC | Delay to first establish PCK | X | X |
PCK and GCLK Ready status issue | X | X | |
PIO | Open drain management limitation | X | X |
ADC | Temperature sensor still enabled when stopped without conversion | X | X |
Temperature sensor spurious activation with CH30 | X | X | |
I2SMCC | Time Division Multiplexed Left Justified (TDMLJ) is not functional in Client mode | X | X |
SSC | Inverted left/right channels | X | X |
TD output delay | X | X | |
SECUMOD | Tamper timestamping polarity error | X | X |
GMAC | GMAC0 not functional with multiple queues in 10/100 Half Duplex mode | X | X |
SDMMC | SDMMC failure when changing speed mode or performing ALL soft reset on-the-fly | X | X |
GCLK cannot be stopped | X | X | |
MCAN | Debug message handling state machine not reset to Idle when CCCR.INIT is set | X | X |
TCPC | Signal level detection not functional | X | – |