9.2 TD output delay

The TD output is delayed by two or three extra system clock cycles when SSC is configured with the following conditions:
  • RCMR.START = Start on falling edge/Start on rising edge/Start on any edge
  • RFMR.FSOS = None (input)
  • TCMR.START = Receive Start

Work Around

None

Affected Device Revisions

A0

A0-D1G

A0-D2G

A1

A1-D5M

A1-D1G

A1-D2G

A1-D4G

XX