4.1 Configure TCD to Use the PLL as a Clock Source

Todo:
  • Edit the CLOCK_OSCHF_crystal_PLL_init() to configure the PLL to use OSCHF as a source and multiply it by 3x
  • Edit the TIMER_TCD0_init() so the TCD uses the PLL as a clock source and creates a PWM signal
  • Plot the PWM signal using a logic analyzer
  1. Edit CLOCK_OSCHF_crystal_PLL_init() so it sets the OSCHF frequency to 16 MHz by adding:
    ccp_write_io((uint8_t *)&CLKCTRL.OSCHFCTRLA, CLKCTRL_FREQSEL_16M_gc);
    Info: The minimum input frequency to the PLL is 16 MHz, and it has a maximum output of 48 MHz.
  2. Set the PLL multiplication factor to 3x by adding the following to CLOCK_OSCHF_crystal_PLL_init():
    ccp_write_io((uint8_t *) &CLKCTRL.PLLCTRLA, CLKCTRL_MULFAC_3x_gc);
    Info: The PLL has two input sources: The OSCHF and XOSCHF. The default source is OSCHF, but the XOSCHF can be configured by setting the Select Source for PLL (SOURCE) bit in the PLL Control A (PLLCTRLA) register.
  3. Edit TIMER_TCD0_init() to include the following to set the PLL as the clock source with no prescaler: 
    TCD0.CTRLA = TCD_CLKSEL_PLL_gc | TCD_CNTPRES_DIV1_gc | TCD_SYNCPRES_DIV1_gc;
  4. Set the TCD to one ramp PWM mode by writing:
    TCD0.CTRLB = TCD_WGMODE_ONERAMP_gc;
  5. Make the PWM signal available on the pins by adding:
    /*Set TCD pins as output*/
PORTA.DIRSET = PIN4_bm | PIN5_bm;
ccp_write_io((uint8_t *) &TCD0.FAULTCTRL, TCD_CMPAEN_bm | TCD_CMPBEN_bm);
  6. Enable the TCD by first ensuring that the Enable Ready (ENRDY) bit in the Status (TCDn.STATUS) register is set to ‘1’ and then setting the ENABLE bit in Control A (TCDn.CTRLA) register: 
    /* Wait for synchronization */
while(!(TCD0.STATUS & TCD_ENRDY_bm))
{
    ;
}
/* Enable TCD0 */
TCD0.CTRLA |= TCD_ENABLE_bm;
    Info: In addition to the configurations that have been set, the TCD is set to increment the duty cycle of WOA by one bit after every period. See ISR(TCD0_OVF_vect) how this is implemented.
  7. Verify that the solution/project builds by selecting the Build Main Project from the top menu bare in MPLAB® X or by pressing the F11 key.
  8. Flash the device by selecting the Make and Program Device Main Project from the top menu bar in MPLAB® X.
  9. Plot the PWM signal using a Logic Analyzer the output for WOA is available on PA4, while the output for WOB is available on PA5.
Result: The PLL and TCD are combined to create a very high-resolution PWM signal. In Figure   1, you can seen that the duty cycle is increased by about 20 ns from 1.4 µs to 1.42 µs after each period showing the high-resolution of the PWM signal.
Figure 4-1. Assignment 2: Result