35.7.4 SPIxCLK

SPI Clock Selection Register

Name:	SPIxCLK
Address:	0x01E3


Bit	7	6	5	4	3	2	1	0
					CLKSEL[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – CLKSEL[3:0] SPI Clock Source Selection

Table 35-5. SPI CLK Source Selections
CLK	Selection
`1111 - 1110`	Reserved
`1101`	CLC4_OUT
`1100`	CLC3_OUT
`1011`	CLC2_OUT
`1010`	CLC1_OUT
`1001`	TU16B_OUT
`1000`	TU16A_OUT
`0111`	TMR4_Postscaler_OUT
`0110`	TMR2_Postscaler_OUT
`0101`	TMR0_OUT
`0100`	Clock Reference Output
`0011`	EXTOSC
`0010`	MFINTOSC (500 kHz)
`0001`	HFINTOSC
`0000`	F_OSC (System Clock)

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