35.7.8 SPIxSTATUS
| Name: | SPIxSTATUS |
| Address: | 0x01DE |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXWE | TXBE | RXRE | CLB | RXBF | |||||
| Access | R/C/HS | R | R/C/HS | S | R | ||||
| Reset | 0 | 1 | 0 | 0 | 0 |
Bit 7 – TXWE Transmit Buffer Write Error
| Value | Description |
|---|---|
| 1 | SPIxTXB was written while TxFIFO was full |
| 0 | No error has occurred |
Bit 5 – TXBE Transmit Buffer Empty
| Value | Description |
|---|---|
| 1 | Transmit buffer TxFIFO is empty |
| 0 | Transmit buffer is not empty |
Bit 3 – RXRE Receive Buffer Read Error
| Value | Description |
|---|---|
| 1 | SPIxRXB was read while RxFIFO was empty |
| 0 | No error has occurred |
Bit 2 – CLB Clear Buffer Control
| Value | Description |
|---|---|
| 1 | Reset the receive and transmit buffers, making both buffers empty |
| 0 | Take no action |
Bit 0 – RXBF Receive Buffer Full
| Value | Description |
|---|---|
| 1 | Receive buffer is full |
| 0 | Receive buffer is not full |