25.5.2 CLKRCLK

Clock Reference Clock Selection Register

Name:	CLKRCLK
Address:	0x101


Bit	7	6	5	4	3	2	1	0
					CLK[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – CLK[3:0] CLKR Clock Selection

Table 25-2. Clock Reference Module Clock Sources
CLK	Clock Source
`1111 - 1011`	Reserved
`1010`	CLC4_OUT
`1001`	CLC3_OUT
`1000`	CLC2_OUT
`0111`	CLC1_OUT
`0110`	EXTOSC
`0101`	SOSC
`0100`	MFINTOSC (32 kHz)
`0011`	MFINTOSC (500 kHz)
`0010`	LFINTOSC
`0001`	HFINTOSC
`0000`	F_OSC

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