23.2.2 Input Buffers on Pads with MVIO

The pads on MVIO domain are equipped with various types of input buffers as listed in Table 23-2.

Table 23-2. Input Buffers on MVIO Pads
Input Buffer VDDIOx Operating Range
Low Voltage

0.95V-1.62V

 Standard

1.62V-3.63V

 Standard

3.63V-5.5V
Standard GPIO Buffers
Low-Voltage Buffer (LVBUF) Yes Yes Yes
Regular ST Buffer – Yes Yes
I2C/SMBus Buffers
I2C Buffer – Yes Yes
SMBus 2.0 Buffer – Yes Yes
SMBus 3.0 Buffer Yes Yes Yes
I3C Buffers
I3C Fast ST (FST) Buffer(1) – Yes –
I3C Low-Voltage (LV) Buffer(2,3) Yes – –
Note:
  1. The maximum VDDIOx operating voltage for I3C-FST buffer is 3.63V.
  2. The I3C-LV buffer has a startup time before becoming fully operational, which is specified in the “Electrical Specifications” chapter. During this time, the output of the buffer is 0 regardless of the status of the corresponding pin.
  3. The 1.4V-1.62V VDDIOx operating range of the I3C LV buffer requires VDD > 2.4V.
  4. Both the I3C and I2C modules are equipped with dedicated 50 ns spike filters on SDA/SCL pads. While the spike filters in the I2C module are always on and can work with all buffers, the spike filters in the I3C module need to be explicitly enabled by the user and are limited to non-I3C buffers only. Refer to the “I3C – Improved Inter-Integrated Circuit Module” chapter for more information.
  5. The VDDIOx Low-Voltage 0.95V-1.62V operation still requires the main device to be powered up with VDD > 1.8V.
  6. Refer to the “Electrical Specifications” chapter for threshold levels for the different input buffers. Some buffers may have VIH specifications higher than the lowest VDDIOx operating voltage.
The input buffers are selected using the I3CBUF and SYSBUF bits in the RxyFEAT register, where Rxy represents the corresponding MVIO pin (like RC0). The I3CBUF bits are used to select an input buffer for the I3C module, whereas the SYSBUF bits are used to select an input buffer for the I2C module, which is also routed as an input selection through the Peripheral Pin Select (PPS) for other modules on the device. The I3CBUF and SYSBUF selections work independently of each other, thus allowing both I3C and I2C to operate on the same bus using the same set of SDA and SCL pins. Refer to the "I/O Ports" chapter for the RxyFEAT register definition.
CAUTION:
  1. If the user configures the SYSBUF bits to select one of the I3C buffers (FST or LV), then the user must also configure the I3CBUF bits to select the same I3C buffer for reliable and predicable operation. However, if the user selects a non-I3C buffer using the SYSBUF bits, then I3CBUF can be configured to select any input buffer.
  2. It is highly recommended for the users to switch input buffers when the module using the buffers is disabled. Switching buffers may cause the input signal to glitch, which may be interpreted as a false Start or Stop condition in the case of I3C and I2C modules.
Remember:
Remember that the I3C SDA and SCL pins are not remappable through PPS on this device. Hence, the input buffer selected using the I3CBUF bits feed into a fixed SDA/SCL pad for one of the I3C modules available on the device. Refer to the “Pin Allocation Table” section in the data sheet for more information on which MVIO pins are designated for I3C SDA and SCL.