23.2.1 POR and Voltage Monitors

To prevent improper operation of the level shifters at low voltage, a Power-on Reset (POR) circuit is included. The POR circuit is automatically enabled on supply power up and holds the corresponding voltage domain logic in reset state until the power supply has reached sufficient voltage for the corresponding voltage domain logic to operate properly. Once this supply voltage is reached, the POR circuit on that voltage domain will power itself down to save power, and re-arm itself if the supply voltage drops too low. For VDD power domain, the device’s main POR circuit is used whereas for VDDIOx domain, a separate POR circuit is included in the MVIO domain. The POR and PORVDDIOx bits in the PCON0 and PCON1 registers are used to represent when the corresponding voltage domain has recovered from a POR reset.

Once the voltage domain logic is released by the POR circuit, it is important to ensure that both the voltage domains (VDD and VDDIOx domains) are powered up and operating at sufficient voltage for the level shifters to work properly. To achieve this, each MVIO domain consists of two voltage monitors:
  1. The first voltage monitor is powered using the main VDD supply and becomes active when VDD reaches a sufficient voltage level. This voltage monitor is used to monitor the VDDIOx voltage level threshold has been achieved for level shifters to work.
  2. The second voltage monitor is powered using the VDDIOx supply and becomes active when VDDIOx reaches a sufficient voltage level. This voltage monitor is used to monitor the main VDD voltage level threshold has been achieved for level shifters to work.

This cross-coupled approach to voltage monitoring ensures that both – the monitor’s current domain and the opposite voltage domain have reached the sufficient voltage for level shifters to operate safely. Refer to Figure 23-1 for clarification. Refer to the Power Sequencing section for different ways to power up both the voltage domains.

Important: To comply with the MIPI I3C® Specification, all the I3C SDA/SCL pads in the MVIO domain are designed to be fail-safe, meaning the pads will not draw excess current when the pad voltage is greater than the VDDIOx supply voltage. Refer to the “Electrical Specifications” chapter for absolute maximum voltage ratings for the I3C pads on MVIO domain.
Figure 23-1. POR and Voltage Monitors on MVIO Domain