37.2.3.2 SDA and SCL Pins
Like I2C, the I3C bus consists of a serial data line (SDA) and a serial clock line (SCL), although the bus voltage, frequency, and signaling may vary. Refer to Table 37-3 for more information.
The I3C SDA and SCL pins on this device are in a different voltage domain powered by the Multi-Voltage I/O (MVIO). The VDDIOx power pin corresponding to the SDA/SCL pins must be powered up to the desired operating voltage level for the device to be present on the I3C bus. Refer to the “MVIO – Multi-Voltage I/O” chapter for more information.
The I3C SDA and SCL pins must be configured as open-drain inputs. Open-drain configuration is accomplished by setting the appropriate bits in the Open-Drain Control (ODCONx) registers, while the input direction is handled by setting the appropriate bits in the Tri-State Control (TRISx) registers. Refer to the “I/O Ports” chapter for more information.
I3C SDA and SCL pads are equipped with a variety of input buffers and output drivers. Refer to the “Input Buffers on Pads with MVIO” and “Output Drivers on Pads with MVIO” sections in the “MVIO - Multi-Voltage I/O” chapter on how to properly select an appropriate input buffer and which output driver drives the SDA/SCL lines. Figure 37-3 and Figure 37-4 depict a summary of settings to properly operate this module in I3C mode and in I2C mode respectively.
This device is equipped with fail-safe pads on the I3C SDA and SCL pins, which are designed to avoid drawing leakage current when the I3C bus voltage is greater than the MVIO supply voltage. Refer to the “Electrical Specifications” chapter for absolute maximum ratings for the MVIO and I3C pins.