23.4.1 MVIOSTAT
Name: | MVIOSTAT |
Address: | 0x4A6 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
VDDIO3RDY | VDDIO2RDY | ||||||||
Access | R | R | |||||||
Reset | u | u |
Bit 1 – VDDIO3RDY VDDIO3 Voltage Monitor Ready
Value | Description |
---|---|
1 | The internal voltage monitor on the VDDIO3 domain is ready, and the VDDIO3 supply voltage is within the acceptable range of operation. The MVIO pin configurations are loaded from the corresponding PORT registers. |
0 | The internal voltage monitor on the VDDIO3 domain is not ready, or the VDDIO3 supply voltage is not within the acceptable range of operation. The MVIO pins are tri-stated. |
Bit 0 – VDDIO2RDY VDDIO2 Voltage Monitor Ready
Value | Description |
---|---|
1 | The internal voltage monitor on the VDDIO2 domain is ready, and the VDDIO2 supply voltage is within the acceptable range of operation. The MVIO pin configurations are loaded from the corresponding PORT registers. |
0 | The internal voltage monitor on the VDDIO2 domain is not ready, or the VDDIO2 supply voltage is not within the acceptable range of operation. The MVIO pins are tri-stated. |