Digital Peripherals

  • Two 16-Bit Pulse-Width Modulators (PWM):
    • Dual outputs for each PWM module
    • Integrated 16-bit timer/counter
    • Double-buffered user registers for duty cycles
    • Right/Left/Center/Variable Aligned modes of operation
    • Multiple clock and Reset signal selections
  • Two 16-Bit Timers (TMR0/1)
  • Two 8-Bit Timers (TMR2/4) with Hardware Limit Timer (HLT)
  • Two 16-Bit Universal Timers (TU16A/16B):
    • New Timer module that combines most of the operations of all legacy timers (TMR0/1/2, SMT, CCP) into one single timer
    • Two 16-bit timers can be chained together to create a combined 32-bit timer
  • Four Configurable Logic Cells (CLC):
    • Integrated combinational and sequential logic
  • One Complementary Waveform Generator (CWG):
    • Rising and falling edge dead-band control
    • Full-bridge, half-bridge, one-channel drive
    • Multiple signal sources
    • Programmable dead band
    • Fault-shutdown input
  • Two Capture/Compare/PWM (CCP) Modules:
    • 16-bit resolution for Capture/Compare modes
    • 10-bit resolution for PWM mode
  • Programmable CRC with Memory Scan:
    • Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B)
    • Calculate 32-bit CRC over any portion of Program Flash Memory
  • Two UART Modules:
    • One module (UART1) supports LIN host and client, DMX mode, DALI gear and device protocols
    • Asynchronous UART, RS-232, RS-485 compatible
    • Automatic and user timed BREAK period generation
    • Automatic checksums
    • Programmable Stop bits (1, 1.5 and 2 Stop bits)
    • Wake-up on BREAK reception
    • DMA compatible
  • One SPI Module:
    • Configurable length bytes
    • Arbitrary length data packets
    • Transmit-without-receive and receive-without-transmit options
    • Transfer byte counter
    • Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities
  • One I2C Module, SMBus, PMBus™ Compatible:
    • Supports Standard mode (100 kHz), Fast mode (400 kHz) and Fast mode Plus (1 MHz) modes of operation
    • 7-bit and 10-bit Addressing modes with Address Masking modes
    • Dedicated address, transmit and receive buffers and DMA capabilities
    • Bus collision detection with arbitration
    • Bus time-out detection and handling
    • I2C, SMBus 2.0 and SMBus 3.0, and 1.8V input level selections
    • Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities
    • Multi-Host mode, including self-addressing
    • Built-in Error Detection and Recovery
  • Up To Two I3C Modules:
    • Supports I3C target device mode only
    • Can be used as an I2C Client module
    • Adheres to MIPI I3C Basic Specification 1.0
    • Supports Target Reset Action (RSTACT) CCC from MIPI I3C Specification 1.1
    • Supports Dynamic Address Assignment, Common Command Codes (CCC), Direct and Broadcast addressing
    • Transfer speeds up to 12.5 Mbps in SDR mode
    • Recognizes HDR Entry and Exit patterns
    • Support for In-Band Interrupt (IBI) and Hot-Join
    • Supports 7-bit configurable target static address
    • I2C backward-compatible with static addressing for I2C transfers
    • Built-in Error Detection and Recovery
  • Device I/O Port Features:
    • 11 I/O pins including two Multi-Voltage I/O (MVIO) pins powered by VDDIO2 (PIC18F04/05/06Q20)
    • 16 I/O pins including two Multi-Voltage I/O (MVIO) pins powered by VDDIO2 and two MVIO pins powered by VDDIO3 (PIC18F14/15/16Q20)
    • MVIO pins support a voltage range of 1.62V through 5.5V
    • Support for 0.95-3.63V I3C communication at up to 12.5 MHz on MVIO pins
    • Individually programmable I/O direction, open-drain, slew rate and weak pull-up control
    • Low-Voltage interface on all I/O pins using LVBUF input buffer
    • Selectable I3C and I2C input buffers on MVIO pins
    • Interrupt-on-change on most pins
    • Three programmable external interrupt pins
  • One Signal Routing Port Module:
    • 8 signal routing pins per module
    • Supports software read/write and customizable input/output control
    • Supports flip-flops and clock source selection for Hardware State Machine and shift register applications
    • Integration with PPS, Interrupt-on-Change and DMA/ADC triggers available
  • Peripheral Pin Select (PPS):
    • Enables pin mapping of digital I/O (except I3C signals)