33.15 ADC

Operating conditions:
  • VDD = 1.8V to 5.5V
  • Temperature = -40°C to 125°C
  • DUTYCYC = 25%
  • CLKADC = 13 × fADC
  • SAMPCAP is 10 pF for 0.55V reference, while it is set to 5 pF for VREF ≥ 1.1V
  • Applies for all allowed combinations of VREF selections and Sample Rates unless otherwise stated
Table 33-23. Power Supply, Reference, and Input Range
SymbolDescriptionConditionsMin.Typ.Max.Unit
VDDSupply voltage 1.8-5.5V
VREFReference voltageREFSEL = Internal reference0.55-VDD - 0.4V
REFSEL = VDD 1.8-5.5
CINInput capacitanceSAMPCAP = 5 pF -5 -pF
SAMPCAP = 10 pF -10 -
RINInput resistance-14-kΩ
VINInput voltage range 0- VREFV
IBANDInput bandwidth1.1V ≤ VREF--57.5 kHz
Table 33-24. Clock and Timing Characteristics
SymbolDescriptionConditionsMin.Typ.Max.Unit
fADCSample rate1.1V ≤ VREF15-115ksps
1.1V ≤ VREF (8-bit resolution)15-150
VREF = 0.55V (10 bits)7.5-20
CLKADC Clock frequency VREF = 0.55V (10 bits)100-260kHz
1.1V ≤ VREF (10 bits)200-1500
1.1V ≤ VREF (8-bit resolution)200-2000(1)
TsSampling time 22 33CLKADC cycles
TCONVConversion time (latency) Sampling time = 2 CLKADC8.7-50 µs
TSTARTStart-up time Internal VREF-22- µs
Note:
  1. 50% duty cycle is required for clock frequencies above 1500 kHz.
Table 33-25. Accuracy Characteristics(2)
SymbolDescriptionConditionsMin.Typ.Max.Unit
RESResolution -10- bit
INLIntegral nonlinearityREFSEL = INTERNAL

VREF = 0.55V		fADC = 7.7 ksps-1.0-LSb
REFSEL = INTERNAL or VDDfADC = 15 ksps-1.0-
REFSEL = INTERNAL or VDD

1.1V ≤ VREF		fADC = 77 ksps-1.0-
fADC = 115 ksps-1.2-
DNL(1)Differential nonlinearityREFSEL = INTERNAL

VREF = 0.55V		fADC = 7.7 ksps-0.6-LSb
REFSEL = INTERNAL or VDDfADC = 15 ksps-0.4-
REFSEL = INTERNAL or VDD

1.1V ≤ VREF		fADC = 77 ksps-0.4-
REFSEL = INTERNAL

1.1V ≤ VREF		fADC = 115 ksps-0.6-
REFSEL = VDD

1.1V ≤ VREF		fADC = 115 ksps-0.6-
EABSAbsolute accuracyREFSEL = INTERNAL

VREF = 1.1V		T = [0, 105]°C

VDD = [1.8V, 3.6V]		-3-LSb
VDD = [1.8V, 3.6V]-3-
REFSEL = VDD-2-
REFSEL = INTERNAL-3-
EGAINGain errorREFSEL = INTERNAL

VREF = 1.1V		T = [0, 105]°C

VDD = [1.8V, 3.6V]		-5-LSb
VDD = [1.8V, 3.6V]-5-
REFSEL = VDD-2-
REFSEL = INTERNAL-5-
EOFFOffset error--0.5-LSb
Note:
  1. A DNL error of ≤ 1 LSb ensures a monotonic transfer function with no missing codes.
  2. These values are based on characterization and not covered by production test limits.