3.4 Clocks

The USART is not continuously clocked; instead, it provides the option to select internal clocks from various sources, including the Slow Clock (SLCK), Main Clock (MAINCK), any available Phase-Locked Loop (PLL) clock, and the Host Clock (MCK). This selection is achieved through the configuration of the Programmable Clock (PMC) Control Status Register's (PMC_PCKx) Clock Source Selection (CSS) field.

Additionally, the frequency of these clock sources can be adjusted by setting the PMC_PCKx Prescaler (PRES). Each programmable clock output (PCKx) can be activated or deactivated by writing a '1' to the corresponding Power Management Controller System Clock Enable Register (PMC_SCER.PCKx) or System Clock Disable Register (PMC_SCDR.PCKx). The operational status of these internal clocks is reflected in the PMC System Clock Status Register (PMC_SCSR.PCKx). The PMC Status Register (PMC_SR. PCKRDYx) flag is used to indicate the readiness of the programmable internal clock after being set in the Programmable Clock Registers. For USART operations, PCK4 is designated.

The Power Management Controller (PMC) governs the clocking of embedded peripherals through the PMC Peripheral Control Register (PMC_PCR). This register enables users to manage the activation and deactivation of various peripheral clocks, including the Peripheral Clocks (periph_clk [PID]), which are distributed to each peripheral and derived from the Host Clock (MCK), and the Generic Clocks (GCLK[PID]), specifically allocated to I2SC0 and I2SC1. These clocks function independently from the core and bus clocks (HCLK, MCK, and periph_clk [PID]) and are generated through the selection and division of sources, such as SLCK, MAINCK, UPLLCKDIV, PLLACK, and MCK. To configure a peripheral's clocks, the PMC_PCR.CMD must be set to '1', and the PMC_PCR.PID must be assigned the index of the targeted peripheral. It is imperative that all other configuration fields are accurately defined for proper setup.