2 Overview

The TCD is a high-performance waveform controller that consists of an asynchronous counter, a prescaler, compare logic, capture logic, and control logic. The TCD contains a counter that can run on a clock that is asynchronous to the system clock. It contains compare logic that can generate two independent outputs with optional dead-time. It is connected to the event system for capture and deterministic fault control. The timer/counter can generate interrupts and events on compare match and overflow.

Figure 2-1. TCD Block Diagram

The TCD core is asynchronous to the system clock. The timer/counter consist of two compare/capture units, each with a separate waveform output. In addition, there are two extra waveform outputs that can be equal to the output from one of the units. The compare registers CMPxSET and CMPxCLR are stored in the respective registers (TCD.CMPxSET, TCD.CMPxCLR), which consist of both a low and a high byte. The registers are synchronized to the TCD domain after writing to the registers. During normal operation, the counter value is continuously compared to the compare registers. This is used to generate both interrupts and events.

The TCD can use the input events in ten different input modes, selected separately for the two input events (see Figure 4-6). The input mode defines how the input event will affect the outputs.