3 Generating Complementary Driving Signals

The 8-bit microcontrollers are commonly used in Switch mode power supplies. This use case shows how the TCD can be configured to generate complementary waveforms for the power MOSFET transistors. In this example, the TCD instance is configured to generate two complementary signals with 50 kHz frequency and 100 ns dead-time.

Figure 3-1. Dual Slope Mode

The maximum counter value is stored in the CMPBLCR register (see Figure 3-1)
The WOA output is set when the TCD counter counts down and matches the CMPASET value
WOA is cleared when the TCD counter counts up and matches the CMPASET value
The WOB output is set when the TCD counter counts up and matches the CMPBSET value
WOB is cleared when the TCD counter counts down and matches the CMPBSET value

The Waveform Generation mode will be set to dual slope using the CTRLB register.
```
TCD0.CTRLB = TCD_WGMODE_DS_gc;
```
Figure 3-2. CTRLB Register
The signal’s period must be deduced from the following formula and written to the CMPBCLR register.
$f_{s i g n a l} = \frac{f_{C L K}}{{P r e s c a l e r}_{C N T} \times 2 \times (C M P B C L R + 1)}$
The peripheral clock will be set as the 20 MHz internal oscillator and the counter prescaler will be set to ‘1’.

$C M P B C L R = \frac{f_{C L K}}{{P r e s c a l e r}_{C N T} \times 2 \times f_{s i g n a l}} - 1 = \frac{20 \times 10^{6}}{1 \times 2 \times 50 \times 10^{3}} - 1 ≅ 200 = 0 x C 8$
```
TCD0.CMPBCLR = 0xC8;
```
To set the dead-time, the counting period must be determined, as well as the number of counting periods that match the dead-time.
${C N T}_{p e r i o d} = \frac{1}{f_{C N T}} = \frac{{\Pr e s c a l e r}_{C N T}}{f_{C L K}} = \frac{1}{20 \times 10^{6}} = 50 n s$

$D e a d t i m e = 2 \times {C N T}_{p e r i o d} = 100 n s$

$Assuming the user wants both signals to have
the same duty cycle.$

$C M P B S E T = \frac{C M P B C L R}{2} + \frac{D e a d t i m e}{2} = 0 x 65$

$C M P A S E T = \frac{C M P B C L R}{2} - \frac{D e a d t i m e}{2} = 0 x 63$
```
TCD0.CMPBSET = 0x65;

TCD0.CMPASET = 0x63;
```
Before enabling the timer, the ENRDY bit of the STATUS register must be verified to have the value ‘1’.
The hardware sets this bit when it is safe to start the timer. This mechanism prevents synchronization issues between the TCD time domain and the system time domain.
```
while(!(TCD0.STATUS & TCD_ENRDY_bm))
{
    ;
}
```
Figure 3-3. STATUS Register
After the ENRDY bit is set, the timer can be enabled from the CTRLA register.
From the same register, the clock source and the prescaler can also be set. All the bits from CTRLA except the ENABLE bit are enable-protected, they can only be written when ENABLE is set to ‘0’ before the writing operation.
```
TCD0.CTRLA = TCD_CLKSEL_20MHZ_gc	
           | TCD_CNTPRES_DIV1_gc
           | TCD_ENABLE_bm;
```
Figure 3-4. CTRLA Register
To enable the output channels, certain bits in the FAULTCTRL register may be set.
This register is under Configuration Change Protection (CCP). Thus, a key must be written in the CCP register of the CPU before writing to the FAULTCTRL register. In this case, only channels A and B will be enabled.
```
void TCD0_enableOutputChannels(void)
{
        CPU_CCP = CCP_IOREG_gc;

        TCD0.FAULTCTRL = TCD_CMPAEN_bm 
                       | TCD_CMPBEN_bm;
}
```
Figure 3-5. FAULTCTRL Register

Info: After a Reset, the FAULTCTRL register loads its value from the fuses.
In the targeted microcontroller, the TCD output channels A and B are linked to PA4 and PA5. These pins must be configured as outputs:
```
PORTA.DIR |= PIN4_bm       
          | PIN5_bm; 
```

This application will configure the TCD instance to generate two complementary signals with 50 kHz frequency and 100 ns dead-time.

Tip: The full code example is also available in the Appendix section.

An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here: