4 Controlling Synchronous Signals Using Input Events

In motor control applications, it is often necessary to use perfectly synchronized signals. Also, there is a narrow class of applications that, for driving purposes, requires just a little bit more current than a pin can provide. In these cases, the possibility to map the same signal on multiple pins can reduce the bill of materials.

In most embedded systems there are different feedback loops and fault control components that ensure everything works properly. For reliability reasons, it is better to design these feedback mechanisms without the use of the MCU core. TCD has two event inputs that can be used to monitor the activity of other peripherals and components, and alter the output accordingly.

In this example, the TCD instance will be configured to generate four PWM signals with 10 kHz frequency and approximately 50% duty cycle, synchronized in pairs. In case of a fault signal on an input channel, the timer will stop and wait until the signal changes to the Safe state (no fault detected).

The timer will be configured from the CTRLB register (as in the previous use case), but this time in the Four Ramp mode:
```
TCD0.CTRLB = TCD_WGMODE_FOURRAMP_gc;
```
Figure 4-1. CTRLB Register

Figure 4-2. Four Ramp Mode
By default, channels C and D are linked to channel A. For the signals to be synchronized in pairs, the CMPDSEL bit from the CTRLC register must be set to link channel D to channel B (see Figure 4-4):
```
TCD0.CTRLC = TCD_CMPDSEL_bm;
```
Figure 4-3. CTRLC Register

Figure 4-4. Full-Bridge Output
The frequency can be computed using the following formula:
$f_{P W M} = \frac{f_{C L K}}{{P r e s c a l e r}_{C N T} \times (C M P A S E T + C M P A C L R + C M P B S E T + C M P B C L R + 4)}$

$C M P A S E T + C M P A C L R + C M P B S E T + C M P B C L R = \frac{f_{C L K}}{f_{\Pr e s c a l e r} \times f_{P W M}} - 4 =$

$= \frac{20000000}{4 \times 10000} - 4 = 496 = 0 x 1 F 0$

The targeted duty cycle is approximately 50%, so CMPACLR = CMPBCLR. For most applications, there is a settling time. Thus, the user must consider that and manually configure the peripheral to include a little dead-time. So CMPASET = CMPBSET = 2 for 0.4 µs settling time:

$C M P A C L R = C M P B C L R = \frac{0 x 1 F 0 - C M P A S E T - C M P B S E T}{2} = \frac{0 x 1 F 0 - 2 - 2}{2} = 0 x F 6$
```
TCD0.CMPASET = 0x02;				

TCD0.CMPACLR = 0xF6; 

TCD0.CMPBSET = 0x02;				

TCD0.CMPBCLR = 0xF6;
```
For fault detection purposes, input channel A of the timer will be configured to be active-low and the digital filter of the channel will be enabled to filter the potential spikes (see Figure 4-5).
For this use case, the fault signal will be externally triggered by the press of a button, connected to pin PC5:
```
TCD0.EVCTRLA = TCD_CFG_FILTER_gc	
             | TCD_EDGE_FALL_LOW_gc
             | TCD_TRIGEI_bm;
```
Figure 4-5. EVCTRL Register
The timer can be configured to respond to the input signal in various ways, using the INPUTCTRLA register.
In this case, when a falling edge is detected on channel A, the timer is stopped and reset. The counter will restart at the next rising edge of the input signal.
Figure 4-6. INPUTCTRLA Register
The ENRDY bit of the STATUS register must be ‘1’ before starting the timer from the CTRLA register.
Also, the 20 MHz clock is selected from CTRLA together with a prescaler of 4.
```
while(!(TCD0.STATUS & TCD_ENRDY_bm))
{
    ;
}

TCD0.CTRLA = TCD_CLKSEL_20MHZ_gc | TCD_CNTPRES_DIV4_gc | TCD_ENABLE_bm;
```
In this example, all four output channels are used. The procedure is detailed within the previous use case.
```
void TCD0_enableOutputChannels(void)
{
        CPU_CCP = CCP_IOREG_gc;		

        TCD0.FAULTCTRL = TCD_CMPAEN_bm | TCD_CMPBEN_bm | TCD_CMPCEN_bm | TCD_CMPDEN_bm;
}
```
The event system needs to be configured to link the event generator to the TCD instance.
In this case, the fault signal is simulated by pressing a button that is connected to PC5. The initialization code is provided below, but the event system configuration details are beyond the scope of this document.
```
void EVENT_SYSTEM_init(void)
{
        EVSYS.ASYNCCH2 = EVSYS_ASYNCCH2_PORTC_PIN5_gc;

        EVSYS.ASYNCUSER6 = EVSYS_ASYNCUSER6_ASYNCCH2_gc;
}
```
Channels A and B are linked with PA4 and PA5 pins, and channels C and D are linked with PC0 and PC1 pins. These pins must be configured as outputs.
PC5, which is configured as input, is connected to the ATtiny817 Xplained Mini user button and has an internal pull-up resistor enabled.
A pull-up resistor provides a default state of ‘1’ to the pin. Thus, the button will be used to drive the pin low (logical ‘0’) when it is pressed.
```
PORTA.DIR |= PIN4_bm      
          | PIN5_bm;    

PORTC.DIR |= PIN0_bm      
          | PIN1_bm;        

PORTC.DIR &= ~PIN5_bm;      

PORTC.PIN5CTRL = PORT_PULLUPEN_bm;  
```

This application will configure the TCD instance to generate four PWM signals with 10 kHz frequency at an approximately 50% duty cycle, synchronized in pairs.

Moreover, when a fault signal appears on an input channel, the timer will stop and wait until the signal changes to the Safe state.

Tip: The full code example is also available in the Appendix section.

An MCC generated code example for AVR128DA48, with the same functionality as the one described in this section, can be found here: