8 Debug Considerations
The SAMA5D27 SOM1 JTAG access is disabled during the execution of the
ROM code sequence. It is re-enabled when jumping into SRAM when a valid code has been found on
an external NVM, at the same time the ROM memory and fuses are hidden. If no valid boot is
found on an external NVM, the ROM code
- enables the USB connection and one UART serial port
- starts the standard SAM-BA monitor
- locks access to the ROM memory
- re-enables the JTAG connection
The SAMA5D27 SOM1 has multiple debug and JTAG settings. For more information, refer to the SAMA5D2 Data Sheet, document no. DS60001476, “SECUMOD JTAG Protection Control Register”, "Customer Fuse Matrix" and "Special Function Bits".
The JTAG I/O set can be configured. For correct operations, the I/O set to be used is JTAG_IOSET_3, i.e., the field JTAG_IO_SET in the Boot Configuration Word must be written with value '2'.(1)
Note: Due to IO conflict on line PA22,
JTAG_IOSET_4 must not be implemented when SDMMC1 is used as an NVM boot media. See the
SAMA5D2 Data Sheet, document no. DS60001476, “Boot Configuration Word”.