2.4 Configuration Bytes

The devices have 13 Configuration Bytes, starting at address 30 0000h. The Configuration bits enable or disable specific features, placing these controls outside the normal software process. They also establish configured values prior to the execution of any software.

CAUTION:

The address location for the Configuration bytes on these devices does not increment sequentially. Refer to the Register Summary for address locations.

In terms of programming, consider the following Configuration bits:
  1. SAFLOCK: Storage Area Flash (SAF) Lock Enable bit (1)
    • 1 = OFF: SAF Lock disabled.
    • 0 = ON: SAF Lock enabled; SAF areas are locked, SAFSZ bits can only be set to ‘0’ but cannot be erased to ‘1’.
  2. LVP: Low-Voltage Programming Enable bit
    • 1 = ON: Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. The MCLRE Configuration bit is ignored.
    • 0 = OFF: High voltage on MCLR/VPP must be used for programming.

    It is important to note that the LVP bit cannot be written (to ‘0’) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode or accidentally eliminating LVP mode from the Configuration state. For more information, refer to the Low-Voltage Programming (LVP) Mode section.

  3. MCLRE: Master Clear (MCLR) Enable bit
    • If LVP = 1: RA3 pin function is MCLR
    • If LVP = 0
      • 1 = RA3 pin is MCLR
      • 0 = RA3 pin function is a port-defined function
  4. CP: User NVM Program Memory Code Protection bit
    • 1 = OFF: User NVM code protection is disabled
    • 0 = ON: User NVM code protection is enabled
  5. CPD: Data EEPROM Code Protection bit
    • 1 = OFF: Data EEPROM code protection is disabled
    • 0 = ON: Data EEPROM code protection is enabled
CAUTION:
  1. Once enabled, the SAFLOCK bit CANNOT be disabled. Bulk Erase and self-erase operations are not possible.