36.3.8 Address Buffers

The I²C module has two address buffer registers, I2CxADB0 and I2CxADB1, which can be used as address receive buffers in Client mode, address transmit buffers in Host mode, or both address transmit and address receive buffers in 7-bit Multi-Host mode (see table below). The address buffers are enabled/disabled via the Address Buffer Disable (ABD) bit.

When the ABD bit is clear (ABD = 0), the buffers are enabled, which means:

• In 7-bit Host mode, the desired client address with the R/W value is transmitted from the I2CxADB1 register, bypassing the I²C Transmit Buffer (I2CxTXB). I2CxADB0 is unused.
• In 10-bit Host mode, I2CxADB1 holds the upper bits and R/W value of the desired client address, while I2CxADB0 holds the lower eight bits of the desired client address. Host hardware copies the contents of I2CxADB1 to the transmit shift register and waits for an ACK from the client. Once the ACK is received, host hardware copies the contents of I2CxADB0 to the transmit shift register.
• In 7-bit Client mode, a matching received address is loaded into I2CxADB0, bypassing the I²C Receive Buffer (I2CxRXB). I2CxADB1 is unused.
• In 10-bit Client mode, I2CxADB0 is loaded with the lower eight bits of the matching received address, while I2CxADB1 is loaded with the upper bits and R/W value of the matching received address.
• In 7-bit Multi-Host mode, the device can be both a host and a client depending on the sequence of events on the bus. When being addressed as a client, the matching received address with R/W value is stored into I2CxADB0. When being used as a host, the desired client address and R/W value are loaded into the I2CxADB1 register.

When the ABD bit is set (ABD = 1), the buffers are disabled, which means:

• In Host mode, the desired client address is transmitted from the I2CxTXB register.
• In Client mode, a matching received address is loaded into the I2CxRXB register.