36.4.2.2 Host Clock Timing

The Serial Clock (SCL) signal is generated by module hardware via the I²C Clock Selection (I2CxCLK) register and the Fast Mode Enable (FME) bit.

I2CxCLK contains several clock source selections. The clock source selections typically include variants of the system clock and timer resources.

Important: When using a timer as the clock source, the timer must also be configured. Additionally, when using the HFINTOSC as a clock source it is important to understand that the HFINTOSC frequency selected by the OSCFRQ register is used as the clock source. The clock divider selected by the NDIV bits is not used. For example, if OSCFRQ selects 4 MHz as the HFINTOSC clock frequency, and the NDIV bits select a divide-by-four scaling factor, the I²C Clock Frequency will be 4 MHz and not 1 MHz since the divider is ignored.

The FME bit acts as a prescaler (clock divider) to the clock source selected by I2CxCLK.

When FME is clear (FME = 0), one SCL period (T_SCL) is equal to five clock periods of the selected I2CxCLK source. In other words, the I2CxCLK source is divided by five. For example, if the MFINTOSC (500 kHz) clock source is selected and the FME bit is clear, the actual SCL frequency is 100 kHz (see Equation below).

Equation 36-1. SCL Frequency (FME = 0)

f_{S C L} = \frac{f_{I 2 C x C L K}}{5}

Example:

I2CxCLK: MFINTOSC (500 kHz)
FME: FME = 0

f_{S C L} = \frac{500 k H z}{5} = 100 k H z

When FME is clear, host hardware uses the first I2CxCLK source period to drive SCL low (see figure below). During the second I2CxCLK period, hardware verifies that SCL is in fact low. During the third period, hardware releases SCL, allowing it to float high. Host hardware then uses the fourth and fifth I2CxCLK periods to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the fourth and/or fifth I2CxCLK period, host hardware samples each successive I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next two I2CxCLK periods to verify that SCL is high.

When FME is set (FME = 1), one SCL period (T_SCL) is equal to four clock periods of the selected I2CxCLK source. In other words, the I2CxCLK source is divided by four. Using the example from above, if the MFINTOSC (500 kHz) clock source is selected and the FME bit is set, the actual SCL frequency is 125 kHz (see Equation below).

Equation 36-2. SCL Frequency (FME = 1)

f_{S C L} = \frac{f_{I 2 C x C L K}}{4}

Example:

I2CxCLK: MFINTOSC (500 kHz)
FME: FME = 1

f_{S C L} = \frac{500 k H z}{4} = 125 k H z

When FME is set, host hardware uses the first I2CxCLK source period to drive SCL low (see figure below). During the second I2CxCLK period, hardware verifies that SCL is in fact low. During the third period, hardware releases SCL, allowing it to float high. Host hardware then uses the fourth I2CxCLK period to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the fourth I2CxCLK period, host hardware samples each successive I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next I2CxCLK period to verify that SCL is high.