36.5.4 I2CxSTAT0

I2C Status Register 0

Note:

This bit holds the R/W bit information following the last received address match. Addresses transmitted by the host do not affect the host’s R bit, and addresses appearing on the bus without a match do not affect the R bit.
I2CxCLK must have a valid clock source selected for this bit to function.

Name:	I2CxSTAT0
Address:	0x0298


Bit	7	6	5	4	3	2	1	0
	BFRE	SMA	MMA	R	D
Access	R	R	R	R	R
Reset	0	0	0	0	0

Bit 7 – BFRE Bus Free Status⁽²⁾

Value	Description
`1`	Indicates an idle bus; both SCL and SDA have been high for the time selected by the BFRET bits
`0`	Bus is not idle

Bit 6 – SMA Client Mode Active Status

Value Description

Value	Description
`1`	Client mode is active Set after the 8th falling SCL edge of a received matching 7-bit client address Set after the 8th falling SCL edge of a matching received 10-bit client low address Set after the 8th falling SCL edge of a received matching 10-bit client high w/read address, only after a previous received matching high and low w/write address
`0`	Client mode is not active Cleared when any Restart/Stop condition is detected on the bus Cleared by BTOIF and BCLIF conditions

1

Client mode is active

Set after the 8th falling SCL edge of a received matching 7-bit client address

Set after the 8th falling SCL edge of a matching received 10-bit client low address

Set after the 8th falling SCL edge of a received matching 10-bit client high w/read address, only after a previous received matching high and low w/write address

0

Client mode is not active

Cleared when any Restart/Stop condition is detected on the bus

Cleared by BTOIF and BCLIF conditions

Bit 5 – MMA Host Mode Active Status

Value	Description
`1`	Host mode is active Set when host state machine asserts a Start condition
`0`	Host mode is not active Cleared when BCLIF is set Cleared when Stop condition is issued Cleared for BTOIF condition after the host successfully shifts out a Stop condition

Bit 4 – R Read Information⁽¹⁾

Value	Description
`1`	Indicates that the last matching received address was a Read request
`0`	Indicates that the last matching received address was a Write request

Bit 3 – D Data

Value	Description
`1`	Indicates that the last byte received or transmitted was data
`0`	Indicates that the last byte received or transmitted was an address

This bit holds the R/W bit information following the last received address match. Addresses transmitted by the host do not affect the host’s R bit, and addresses appearing on the bus without a match do not affect the R bit. I2CxCLKI2CxCLK must have a valid clock source selected for this bit to function.