36.5.10 I2CxCNT

I2C Byte Count Register

Note:

It is recommended to write this register only when the module is idle (MMA = 0 or SMA = 0) or when the module is clock stretching (CSTR =1 or MDR = 1).
CNTIF is set on the 9th falling SCL edge when I2CxCNT = 0.

Name:	I2CxCNT
Address:	0x028D


Bit	7	6	5	4	3	2	1	0
	CNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	x	x	x	x	x	x	x	x

Bits 7:0 – CNT[7:0] I²C Byte Count Register^(1,2)

Reset States:

POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Name	Description
If receiving data:	Count value decremented on 8th falling SCL edge when a new byte is loaded into I2CxRXB
If transmitting data:	Count value is decremented on the 9th falling SCL edge when a new byte is moved from I2CxTXB

It is recommended to write this register only when the module is idle (MMAHost Mode Active Status = 0 or SMAClient Mode Active Status = 0) or when the module is clock stretching (CSTR Client Clock Stretching(3) =1 or MDR Host Data Request (Host pause) = 1). CNTIF Byte Count Interrupt Flag(1) is set on the 9th falling SCL edge when I2CxCNT = 0.

36.5.10 I2CxCNT

Bits 7:0 – CNT[7:0] I2C Byte Count Register(1,2)

Bits 7:0 – CNT[7:0] I²C Byte Count Register^(1,2)