1.4 ADC Clock and Conversion Timing

The ADC can prescale the system clock to provide an ADC clock that is between 50 kHz and 200 kHz to get maximum resolution. If an ADC resolution less than 10 bits is required, the ADC clock frequency can be higher than 200 kHz, but it is not recommended to use an ADC clock with a frequency higher than 1 MHz. At 1 MHz we can expect maximum 8 bits of resolution.

The prescaler value is selected by writing the ADC Prescaler Select bit group in the ADC Control and Status A register (ADCSRA.ADPS) accordingly. When initiating a single-ended conversion by writing the ADC Start Conversion bit in ADCSRA (ADCSRA.ADSC), the conversion starts at the following rising edge of the ADC clock cycle.

The timing for ADC clock and conversion varies slightly for ATtiny88.

ATtiny88:
  1. If an ADC resolution less than 10 bits is required, then the ADC clock frequency can be higher than 200 kHz.
  2. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.