3.1 I/O Multiplexing


VQFN64/ TQFP64	VQFN48/ TQFP48	VQFN32/ TQFP32	SOIC28/ SSOP28/SPDIP28	Pin name^(1,2)	Special	ADC0	ACn	DAC0	OPAMP	ZCDn	USARTn	SPIn	TWIn⁽⁴⁾	TCAn	TCBn	TCD0	EVSYS	CCL
62	44	30	22	PA0	XTALHF1 EXTCLK						0, TxD			0, WO0				LUT0, IN0
63	45	31	23	PA1	XTALHF2						0, RxD			0, WO1				LUT0, IN1
64	46	32	24	PA2	TWI Fm+						0, XCK		0, SDA(HC)	0, WO2	0, WO		EVOUTA	LUT0, IN2
1	47	1	25	PA3	TWI Fm+						0, XDIR		0, SCL(HC)	0, WO3	1, WO			LUT0, OUT
2	48	2	26	PA4							0, TxD⁽³⁾	0, MOSI		0, WO4		WOA
3	1	3	27	PA5							0, RxD⁽³⁾	0, MISO		0, WO5		WOB
4	2	4	28	PA6							0, XCK⁽³⁾	0, SCK				WOC		LUT0, OUT⁽³⁾
5	3	5	1	PA7	CLKOUT		0, OUT 1, OUT 2, OUT			0, OUT 1, OUT 2, OUT	0, XDIR⁽³⁾	0, SS				WOD	EVOUTA⁽³⁾
6				VDD
7				GND
8	4			PB0							3, TxD			0, WO0⁽³⁾ 1, WO0				LUT4, IN0
9	5			PB1							3, RxD			0, WO1⁽³⁾ 1, WO1				LUT4, IN1
10	6			PB2	TWI						3, XCK		1, SDA(HC)⁽³⁾	0, WO2⁽³⁾ 1, WO2			EVOUTB	LUT4, IN2
11	7			PB3	TWI						3, XDIR		1, SCL(HC)⁽³⁾	0, WO3⁽³⁾ 1, WO3				LUT4, OUT
12	8			PB4							3, TxD⁽³⁾	1, MOSI⁽³⁾		0, WO4⁽³⁾ 1, WO4	2, WO⁽³⁾	WOA⁽³⁾
13	9			PB5							3, RxD⁽³⁾	1, MISO⁽³⁾		0, WO5⁽³⁾ 1, WO5	3, WO	WOB⁽³⁾
14				PB6							3, XCK⁽³⁾	1, SCK⁽³⁾	1, SDA(C)⁽³⁾			WOC⁽³⁾		LUT4, OUT⁽³⁾
15				PB7							3, XDIR⁽³⁾	1, SS⁽³⁾	1, SCL(C)⁽³⁾			WOD⁽³⁾	EVOUTB⁽³⁾
16	10	6	2	PC0							1, TxD	1, MOSI		0, WO0⁽³⁾	2, WO			LUT1, IN0
17	11	7	3	PC1							1, RxD	1, MISO		0, WO1⁽³⁾	3, WO⁽³⁾			LUT1, IN1
18	12	8	4	PC2	TWI Fm+						1, XCK	1, SCK	0, SDA(HC)⁽³⁾	0, WO2⁽³⁾			EVOUTC	LUT1, IN2
19	13	9	5	PC3	TWI Fm+						1, XDIR	1, SS	0, SCL(HC)⁽³⁾	0, WO3⁽³⁾				LUT1, OUT
20	14	10	6	VDDIO2
21	15			GND
22	16			PC4							1, TxD⁽³⁾	1, MOSI⁽³⁾		0, WO4⁽³⁾ 1, WO0⁽³⁾
23	17			PC5							1, RxD⁽³⁾	1, MISO⁽³⁾		0, WO5⁽³⁾ 1, WO1⁽³⁾
24	18			PC6			0, OUT⁽³⁾ 1, OUT⁽³⁾ 2, OUT⁽³⁾				1, XCK⁽³⁾	1, SCK⁽³⁾	0, SDA(C)⁽³⁾	1, WO2⁽³⁾				LUT1, OUT⁽³⁾
25	19			PC7						0, OUT⁽³⁾ 1, OUT⁽³⁾ 2, OUT⁽³⁾	1, XDIR⁽³⁾	1, SS⁽³⁾	0, SCL(C)⁽³⁾				EVOUTC⁽³⁾
26	20			PD0		AIN0	0, AINN1 1, AINN1 2, AINN1							0, WO0⁽³⁾				LUT2, IN0
27	21	11	7	PD1		AIN1			OP0, INP	0, ZCIN				0, WO1⁽³⁾				LUT2, IN1
28	22	12	8	PD2		AIN2	0, AINP0 1, AINP0 2, AINP0		OP0, OUT					0, WO2⁽³⁾			EVOUTD	LUT2, IN2
29	23	13	9	PD3		AIN3	0, AINN0 1, AINP1		OP0, INN					0, WO3⁽³⁾				LUT2, OUT
30	24	14	10	PD4		AIN4	1, AINP2 2, AINP1		OP1, INP					0, WO4⁽³⁾
31	25	15	11	PD5		AIN5	1, AINN0		OP1, OUT					0, WO5⁽³⁾
32	26	16	12	PD6		AIN6	0, AINP3 1, AINP3 2, AINP3	OUT										LUT2, OUT⁽³⁾
33	27	17	13	PD7	VREFA	AIN7	0, AINN2 1, AINN2 2, AINN0/AINN2		OP1, INN								EVOUTD⁽³⁾
34	28	18	14	AVDD
35	29	19	15	AGND
36	30			PE0		AIN8	0, AINP1				4, TxD	0, MOSI⁽³⁾		0, WO0⁽³⁾
37	31			PE1		AIN9	2, AINP2		OP2, INP		4, RxD	0, MISO⁽³⁾		0, WO1⁽³⁾
38	32			PE2		AIN10	0, AINP2		OP2, OUT		4, XCK	0, SCK⁽³⁾		0, WO2⁽³⁾			EVOUTE
39	33			PE3		AIN11			OP2, INN	1, ZCIN	4, XDIR	0, SS⁽³⁾		0, WO3⁽³⁾
40				PE4		AIN12					4, TxD⁽³⁾			0, WO4⁽³⁾ 1, WO0⁽³⁾
41				PE5		AIN13					4, RxD⁽³⁾			0, WO5⁽³⁾ 1, WO1⁽³⁾
42				PE6		AIN14					4, XCK⁽³⁾			1, WO2⁽³⁾
43				PE7		AIN15				2, ZCIN	4, XDIR⁽³⁾						EVOUTE⁽³⁾
44	34	20	16	PF0	XTAL32K1	AIN16⁽⁵⁾					2, TxD			0, WO0⁽³⁾		WOA⁽³⁾		LUT3, IN0
45	35	21	17	PF1	XTAL32K2	AIN17⁽⁵⁾					2, RxD			0, WO1⁽³⁾		WOB⁽³⁾		LUT3, IN1
46	36	22		PF2	TWI Fm+	AIN18⁽⁵⁾					2, XCK		1, SDA(HC)	0, WO2⁽³⁾		WOC⁽³⁾	EVOUTF	LUT3, IN2
47	37	23		PF3	TWI Fm+	AIN19⁽⁵⁾					2, XDIR		1, SCL(HC)	0, WO3⁽³⁾		WOD⁽³⁾		LUT3, OUT
48	38	24		PF4		AIN20⁽⁵⁾					2, TxD⁽³⁾			0, WO4⁽³⁾	0, WO⁽³⁾
49	39	25		PF5		AIN21⁽⁵⁾					2, RxD⁽³⁾			0, WO5⁽³⁾	1, WO⁽³⁾
50	40	26	18	PF6⁽⁶⁾	RESET
51	41	27	19	UPDI	UPDI
52				PG0							5, TxD			0, WO0⁽³⁾ 1, WO0⁽³⁾				LUT5, IN0
53				PG1							5, RxD			0, WO1⁽³⁾ 1, WO1⁽³⁾				LUT5, IN1
54				PG2							5, XCK			0, WO2⁽³⁾ 1, WO2⁽³⁾			EVOUTG	LUT5, IN2
55				PG3							5, XDIR			0, WO3⁽³⁾ 1, WO3⁽³⁾	4, WO			LUT5, OUT
56	42	28	20	VDD
57	43	29	21	GND
58				PG4							5, TxD⁽³⁾	0, MOSI⁽³⁾		0, WO4⁽³⁾ 1, WO4⁽³⁾		WOA⁽³⁾
59				PG5							5, RxD⁽³⁾	0, MISO⁽³⁾		0, WO5⁽³⁾ 1, WO5⁽³⁾		WOB⁽³⁾
60				PG6							5, XCK⁽³⁾	0, SCK⁽³⁾				WOC⁽³⁾		LUT5, OUT⁽³⁾
61				PG7							5, XDIR⁽³⁾	0, SS⁽³⁾				WOD⁽³⁾	EVOUTG⁽³⁾

Note:

Pin names are of type Pxn, with x being the PORT instance (A, B, C, ...) and n the pin number. Notation for signals is PORTx_PINn. All pins can be used as event inputs.
All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous detection.
Alternative pin positions.
TWI pins are marked HC if they can be used as TWI Host or Client pins, and C if they can only be used as TWI Client pins.
AIN16 - AIN21 cannot be used as a negative ADC input for differential measurements.
Input only.

AVR® DB

3.1 I/O Multiplexing