15.3.3 NVMREG Erase of Program Memory

Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write to program memory. To erase a program memory row:

Clear the NVMREGS bit to erase program memory locations, or set the NMVREGS bit to erase User ID locations.
Write the desired address into the NVMADRH:NVMADRL register pair.
Set the FREE and WREN bits.
Perform the unlock sequence as described in the “NVM Unlock Sequence” section.

If the program memory address is write-protected, the WR bit will be cleared and the erase operation will not take place.

While erasing program memory, CPU operation is suspended, and resumes when the operation is complete. Upon completion, the NVMIF bit is set, and an interrupt will occur if the NVMIE bit is also set.

Write latch data is not affected by erase operations, and WREN will remain unchanged.

Figure 15-3. NVM Erase Sequence

Note:

See Figure 15-2.

Erasing One Row of Program Flash Memory


; This sample row erase routine assumes the following:
  ; 1.A valid address within the erase row is loaded in variables ADDRH:ADDRL
  ; 2.ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

   BANKSEL    NVMADRL
   MOVF       ADDRL,W
   MOVWF      NVMADRL            ; Load lower 8 bits of erase address boundary
   MOVF       ADDRH,W
   MOVWF      NVMADRH            ; Load upper 6 bits of erase address boundary
   BCF        NVMCON1,NVMREGS    ; Choose PFM memory area
   BSF        NVMCON1,FREE       ; Specify an erase operation
   BSF        NVMCON1,WREN       ; Enable writes
   BCF        INTCON,GIE         ; Disable interrupts during unlock sequence

    ; ---------------------REQUIRED UNLOCK SEQUENCE:--------------------

   MOVLW      0x55               ; Load 0x55 to get ready for unlock sequence
   MOVWF      NVMCON2            ; First step is to load 0x55 into NVMCON2
   MOVLW      0xAA               ; Second step is to load 0xAA into W
   MOVWF      NVMCON2            ; Third step is to load 0xAA into NVMCON2
   BSF        NVMCON1,WR         ; Final step is to set WR bit
	
   ; ------------------------------------------------------------------

   BSF        INTCON,GIE         ; Re-enable interrupts, erase is complete
   BCF        NVMCON1,WREN       ; Disable writes

Table 15-1. NVM Organization and Access Information
Master Values			NVMREG Access			FSR Access
Memory Function	Memory Type	Program Counter (PC), ICSP™ Address	NVMREGS bit (NVMCON1)	NVMADR[14:0]	Allowed Operations	FSR Address	FSR Programming Access
Reset Vector	Program Flash Memory	0x0000	`0`	0x0000	Read/Write	0x8000	Read-Only
User Memory		0x0001	`0`	0x0001		0x8001
User Memory		0x0003	`0`	0x0003		0x8003
INT Vector		0x0004	`0`	0x0004		0x8004
User Memory		0x0005	`0`	0x0005		0x8005
User Memory		0x3FFF⁽¹⁾	`0`	0x3FFF⁽¹⁾		0xFFFF
User ID	Program Flash Memory	0x8000	`1`	0x0000	Read/Write	No Access
User ID	Program Flash Memory	0x8003	`1`	0x0003	Read/Write
Reserved	—	—	—	0x0004	—
Revision ID	Hard Coded in Program Flash Memory	0x8005	`1`	0x0005	Read
Device ID	Hard Coded in Program Flash Memory	0x8006	`1`	0x0006	Read
CONFIG1	Program Flash Memory	0x8007	`1`	0x0007	Read/Write
CONFIG2		0x8008	`1`	0x0008
CONFIG3		0x8009	`1`	0x0009
CONFIG4		0x800A	`1`	0x000A
CONFIG5		0x800B	`1`	0x000B
DIA and DCI	Hard Coded in Program Flash Memory	0x8100	`1`	0x0100	Read
DIA and DCI	Hard Coded in Program Flash Memory	0x82FF	`1`	0x02FF	Read
Reserved	—	0xF000	—	0x7000	—	0x7000	—
Reserved	—	0xF0FF	—	0x7FFF	—	0x7FFF	—

Note:

The maximum Program Flash Memory address for the 0x3FFF family is 0x07FF.