16.2 DMA Organization

The DMA module is designed to move data by using the existing instruction bus and data bus without the need for any dual-porting of memory or peripheral systems (Figure 16-1). The DMA accesses the required bus when granted by the system arbiter.

Figure 16-1. DMA Functional Block Diagram

Depending on the priority of the DMA with respect to CPU execution (refer to the “Memory Access Scheme” section in the “PIC18 CPU” chapter for more information), the DMA Controller can move data through two methods:

Stalling the CPU execution until it has completed its transfers (DMA has higher priority over the CPU in this mode of operation)
Utilizing unused CPU cycles for DMA transfers (CPU has higher priority over the DMA in this mode of operation). Unused CPU cycles are referred to as bubbles, which are instruction cycles available for use by the DMA to perform read and write operations. In this way, the effective bandwidth for handling data are increased; at the same time, DMA operations can proceed without causing a processor stall.