47.2.2 Extended Instruction Set

0 ≤ k ≤ 63

(FSR2) + k → FSR2
(TOS) → PC

The 6-bit literal ‘k’ is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f_n = 3 (binary ‘11’); it operates only on FSR2.

0 ≤ z_s ≤ 127
0 ≤ f_d ≤ 4095

((FSR2) + z_s) → f_d

The contents of the source register are moved to destination register ‘f_d’. The actual address of the source register is determined by adding the 7-bit literal offset ‘z_s’ in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal ‘f_d’ in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh).

0 ≤ z_s ≤ 127
0 ≤ f_d ≤ 16383

((FSR2) + z_s) → f_d

The contents of the source register are moved to destination register ‘f_d’. The actual address of the source register is determined by adding the 7-bit literal offset ‘z_s’ in the first word to the value of FSR2 (14 bits). The address of the destination register is specified by the 14-bit literal ‘f_d’ in the second word. Both addresses can be anywhere in the 16 Kbyte data space (0000h to 3FFFh). The MOVSFL instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h.

0 ≤ z_s ≤ 127
0 ≤ z_d ≤ 127

((FSR2) + z_s) → ((FSR2) + z_d)

The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets ‘z_s’ or ‘z_d’ respectively to the value of FSR2. Both registers can be located anywhere in the 16 Kbyte data memory space (0000h to 3FFFh).

The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register.

If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP.

0 ≤ k ≤ 255

k → FSR2
(FSR2) – 1 → FSR2

The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack.

0 ≤ k ≤ 63

(FSR2) – k → FSR2
(TOS) → PC

The 6-bit literal ‘k’ is subtracted from the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f_n = 3 (binary ‘11’); it operates only on FSR2.