47.2.1 Extended Instruction Syntax

Most of the extended instructions use indexed arguments, using one of the File Select registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets (“[ ]”). This is done to indicate that the argument is used as an index or offset. MPASM™ Assembler will flag an error if it determines that an index or offset value is not bracketed.

When the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Extended Instruction Syntax with Standard PIC18 Commands.

Table 47-3. Extensions to the PIC18 Instruction Set
Mnemonic, Operands		Description	Cycles	16-Bit Instruction Word				Status Affected	Notes
Mnemonic, Operands		Description	Cycles	MSb			LSb	Status Affected	Notes
ADDULNK	k	Add literal to FSR2 and return	2	`1110`	`1000`	`11kk`	`kkkk`	None	1, 3
MOVSF	z_s, f_d	Move z_s (12-bit source) to f_d (12-bit destination)	2	`1110`	`1011`	`0z_sz_sz_s`	`z_sz_sz_sz_s`	None	2, 3, 4
MOVSF	z_s, f_d	Move z_s (12-bit source) to f_d (12-bit destination)	2	`1111`	`f_df_df_df_d`	`f_df_df_df_d`	`f_df_df_df_d`	None	2, 3, 4
MOVSFL	z_s, f_d	Move z_s (14-bit source) to f_d (14-bit destination)	3	`0000`	`0000`	`0000`	`0010`	None	2, 3
				`1111`	`xxxz_s`	`z_sz_sz_sz_s`	`z_sz_sf_df_d`
				`1111`	`f_df_df_df_d`	`f_df_df_df_d`	`f_df_df_df_d`
MOVSS	z_s, z_d	Move z_s (source) to z_d (destination)	2	`1110`	`1011`	`1z_sz_sz_s`	`z_sz_sz_sz_s`	None	2, 3
MOVSS	z_s, z_d	Move z_s (source) to z_d (destination)	2	`1111`	`xxxx`	`xz_dz_dz_d`	`z_dz_dz_dz_d`	None	2, 3
PUSHL	k	Store literal at FSR2, decrement FSR2	1	`1110`	`1010`	`kkkk`	`kkkk`	None	3
SUBULNK	k	Subtract literal from FSR2 and return	2	`1110`	`1001`	`11kk`	`kkkk`	None	1, 3
Note: If Program Counter (PC) is modified or a conditional test is true, the instruction requires an additional cycle. The extra cycle is executed as a `NOP`. Some instructions are multi-word instructions. The extra words of these instructions will be decoded as a `NOP`, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. Only available when extended instruction set is enabled. f_s and f_d do not cover the full memory range. 2 MSbs of bank selection are forced to `0b00` to limit the range of these instructions to lower 4k addressing space.