22.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Offset: 0x0D8

Bit 76543210 
 D1S[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxxx 

Bits 7:0 – D1S[7:0] CLCn Data1 Input Selection

Table 22-2. CLC Input Selection
DyS Input Source DyS (cont.) Input Source (cont.) DyS (cont.) Input Source (cont.)
[0] 0000 0000 CLCIN0PPS [32] 0010 0000 CCP2 [64] 0100 0000 SPI1_SDO
[1] 0000 0001 CLCIN1PPS [33] 0010 0001 CCP3 [65] 0100 0001 SPI1_SCK
[2] 0000 0010 CLCIN2PPS [34] 0010 0010 PWM1S1P1_OUT [66] 0100 0010 SPI1_SS
[3] 0000 0011 CLCIN3PPS [35] 0010 0011 PWM1S1P2_OUT [67] 0100 0011 SPI2_SDO
[4] 0000 0100 CLCIN4PPS [36] 0010 0100 PWM2S1P1_OUT [68] 0100 0100 SPI2_SCK
[5] 0000 0101 CLCIN5PPS [37] 0010 0101 PWM2S1P2_OUT [69] 0100 0101 SPI2_SS
[6] 0000 0110 CLCIN6PPS [38] 0010 0110 PWM3S1P1_OUT [70] 0100 0110 I2C_SCL
[7] 0000 0111 CLCIN7PPS [39] 0010 0111 PWM3S1P2_OUT [71] 0100 0111 I2C_SDA
[8] 0000 1000 FOSC [40] 0010 1000 PWM4S1P1_OUT [72] 0100 1000 CWG1A
[9] 0000 1001 HFINTOSC(1) [41] 0010 1001 PWM4S1P2_OUT [73] 0100 1001 CWG1B
[10] 0000 1010 LFINTOSC(1) [42] 0010 1010 NCO1 [74] 0100 1010 CWG2A
[11] 0000 1011 MFINTOSC(1) [43] 0010 1011 NCO2 [75] 0100 1011 CWG2B
[12] 0000 1100 MFINTOSC (32 kHz)(1) [44] 0010 1100 NCO3 [76] 0100 1100 CWG3A
[13] 0000 1101 SFINTOSC (1 MHz)(1) [45] 0010 1101 CMP1_OUT [77] 0100 1101 CWG3B
[14] 0000 1110 SOSC(1) [46] 0010 1110 CMP2_OUT ... —
[15] 0000 1111 EXTOSC(1) [47] 0010 1111 ZCD ... —
[16] 0001 0000 ADCRC(1) [48] 0011 0000 IOC ... —
[17] 0001 0001 CLKR [49] 0011 0001 DSM1 ... —
[18] 0001 0010 TMR0 [50] 0011 0010 HLVD_OUT ... —
[19] 0001 0011 TMR1 [51] 0011 0011 CLC1 ... —
[20] 0001 0100 TMR2 [52] 0011 0100 CLC2 ... —
[21] 0001 0101 TMR3 [53] 0011 0101 CLC3 ... —
[22] 0001 0110 TMR4 [54] 0011 0110 CLC4 ... —
[23] 0001 0111 TMR5 [55] 0011 0111 CLC5 ... —
[24] 0001 1000 TMR6 [56] 0011 1000 CLC6 ... —
[25] 0001 1001 TU16A [57] 0011 1001 CLC7 ... —
[26] 0001 1010 TU16B [58] 0011 1010 CLC8 ... —
[27] 0001 1011 — [59] 0011 1011 U1TX ... —
[28] 0001 1100 — [60] 0011 1100 U2TX ... —
[29] 0001 1101 — [61] 0011 1101 U3TX ... —
[30] 0001 1110 SMT1 [62] 0011 1110 U4TX ... —
[31] 0001 1111 CCP1 [63] 0011 1111 U5TX [127] 0111 1111 —
Note:
  1. Requests clock.
Reset States: 
POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu