22.8.3 CLCnPOL

Signal Polarity Control Register
Name: CLCnPOL
Offset: 0x0D7

Bit 76543210 
 POL   G4POLG3POLG2POLG1POL 
Access R/WR/WR/WR/WR/W 
Reset 0xxxx 

Bit 7 – POL CLCxOUT Output Polarity Control

ValueDescription
1 The output of the logic cell is inverted
0 The output of the logic cell is not inverted

Bits 0, 1, 2, 3 – GyPOL Gate Output Polarity Control

Reset States: 
POR/BOR = xxxx
All Other Resets = uuuu
ValueDescription
1 The gate output is inverted when applied to the logic cell
0 The output of the gate is not inverted