18.4.4 PMD3

PMD Control Register 3
Note:
  1. Subject to the value of the ZCD Configuration bit.
Name: PMD3
Offset: 0x063

Bit 76543210 
 ACTMDDAC1MDADCMD  C2MDC1MDZCDMD 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 7 – ACTMD Disable Active Clock Tuning

ValueDescription
1 Active Clock Tuning disabled
0 Active Clock Tuning enabled

Bit 6 – DAC1MD Disable Digital-to-Analog Converter

ValueDescription
1 DAC module disabled
0 DAC module enabled

Bit 5 – ADCMD Disable Analog-to-Digital Converter

ValueDescription
1 ADC module disabled
0 ADC module enabled

Bit 2 – C2MD Disable Comparator 2

ValueDescription
1 CM2 module disabled
0 CM2 module enabled

Bit 1 – C1MD Disable Comparator 1

ValueDescription
1 CM1 module disabled
0 CM1 module enabled

Bit 0 – ZCDMD  Disable Zero-Cross Detect(1)

ValueDescription
1 ZCD module disabled
0 ZCD module enabled
Subject to the value of the ZCD Configuration bit.