8.5.14 CRC Boot Expected
Value
The Expected Value for
the CRC of the boot block segment of memoryNote: The CRC-on-boot module uses a 32-bit
polynomial, as such the expected value spans from CONFIG20 to CONFIG23, with the MSB
of CONFIG20 being the MSB of the expected value, and the LSB of CONFIG23 being the
LSB of the expected value.
| Name: | CRC Boot Expected
Value |
| Offset: | 30 0013h |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | BCRCERES[31:24] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | BCRCERES[23:16] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | BCRCERES[15:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | BCRCERES[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 31:0 – BCRCERES[31:0] Boot Block Area CRC
Expected Result
